DATASHEET
PORTABLE CONSUMER CODEC
LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC
ACS422x00
FEATURES
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High fidelity 24-bit stereo CODEC
•
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DAC 102dB SNR; THD+N better than -82dB
ADC 90dB SNR, THD + N better than -80dB
3D stereo enhancement
Dual (cascaded) stereo 6-band parametric equalizers
Programmable Compressor/Limiter/Expander
Psychoacoustic Bass and Treble enhancement
processing
DESCRIPTION
The ACS422x00 is a low-power, high-fidelity integrated
CODEC targeted at portable applications such as tablet
computers, personal navigation devices, portable projec-
tors and speaker docks.
In addition to a high-fidelity
low-power CODEC, the device integrates a DDX
TM
class-D speaker amplifier, a true cap-less headphone
amplifier, and four programmable system PLLs to enable
the timing management of the systems applications pro-
cessor, USB interface, secondary audio and other subsys-
tems. Beyond high-fidelity for portable systems, the device
offers an enriched “audio presence” through built-in audio
processing capability The ACS422x00 has been designed
with rapid customization in mind. IDT is able to rapidly pro-
vide varying levels of integration, additional audio process-
ing, more or fewer PLLs, etc, according to the needs of
large markets or customers.
•
Built in audio controls and processing
•
•
•
•
•
Filterless Stereo DDX
TM
Class D
Speaker Driver
•
•
•
•
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1W/channel (8) or 2W/channel
(4), 0.05% THD+N typical
Tri-state DDX
TM
Class D achieves low EMI and high
efficiency
>80% efficiency at 1W
Spread spectrum support for reduced EMI output power
mode
Anti-Pop circuitry
35 mW output power (16)
Charge-pump allows true ground centered outputs
SNR of 102dB
TARGET APPLICATIONS
•
•
•
•
•
Tablet Computers
Portable Navigation Devices
Personal Media Players
Portable Projectors
Speaker Docks
•
On-chip true cap-less headphone driver
•
•
•
•
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I2S data interface
Microphone/line-in interface
•
•
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Analog microphone or line-in inputs
Digital microphone (ACS422D00)
Automatic level control
•
4 on-chip low-jitter PLLs for internal and system
timing
•
•
Multiple frequency options
Spread spectrum support
1.7 V CODEC supports 1Vrms
Very low standby and no-signal power consumption
1.8V digital / 1.7V analog supply for low power
•
Low power with built in power management
•
•
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2-wire (I
2
C compatible) control interface
68-pin dual row 6x6 mm Thermal Leadless Array
package
DDX
TM
and the DDX logo are trademarks of Apogee Technology.
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.6 08/13
ACS422X00
ACS422x00
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
TABLE OF CONTENTS
1. OVERVIEW ................................................................................................................................ 8
1.1. Block Diagram ...................................................................................................................................8
1.2. Audio Outputs ....................................................................................................................................8
1.3. Audio Inputs .......................................................................................................................................9
1.4. On-Chip PLLs ....................................................................................................................................9
2. POWER MANAGEMENT ........................................................................................................ 10
2.1. Control Registers .............................................................................................................................10
2.2. Stopping the Master Clock ...............................................................................................................11
3. OUTPUT AUDIO PROCESSING ............................................................................................. 12
3.1. DC Removal ....................................................................................................................................12
3.2. Volume Control ................................................................................................................................13
3.3. Digital DAC Volume Control .............................................................................................................14
3.4. Parametric Equalizer .......................................................................................................................14
3.4.1. Prescaler & Equalizer Filter ...............................................................................................15
3.4.2. EQ Registers ......................................................................................................................16
3.4.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM .......................................17
3.5. Gain and Dynamic Range Control ...................................................................................................20
3.6. Limiter ..............................................................................................................................................21
3.7. Compressor .....................................................................................................................................21
3.7.1. Configuration ......................................................................................................................22
3.7.2. Controlling parameters .......................................................................................................23
3.7.3. Overview ............................................................................................................................23
3.7.4. Limiter/Compressor Registers ............................................................................................25
3.7.5. Expander Registers ...........................................................................................................27
3.8. Output Effects ..................................................................................................................................28
3.9. Stereo Depth (3-D) Enhancement ...................................................................................................28
3.10. Psychoacoustic Bass Enhancement ..............................................................................................29
3.11. Treble Enhancement .....................................................................................................................30
3.12. Mute and De-Emphasis .................................................................................................................31
3.13. Mono Operation and Phase Inversion ...........................................................................................31
3.13.1. DAC Control Register .....................................................................................................31
3.13.2. Interpolation and Filtering ................................................................................................32
3.14. Analog Outputs ..............................................................................................................................33
3.14.1. Headphone Output ...........................................................................................................33
3.14.2. Speaker Outputs ..............................................................................................................34
3.14.3. DDX
TM
Class D Audio Processing ....................................................................................34
3.15. Other Output Capabilities ..............................................................................................................39
3.15.1. Audio Output Control .......................................................................................................40
3.15.2. Headphone Switch ...........................................................................................................40
3.15.3. Headphone Operation ......................................................................................................41
3.15.4. EQ Operation ...................................................................................................................41
3.16. Thermal Shutdown .........................................................................................................................42
3.16.1. Algorithm description: ......................................................................................................42
3.16.2. Thermal Trip Points. .........................................................................................................42
3.16.3. Temperature Limit State Diagram: ...................................................................................43
3.16.4. Instant Cut Mode ..............................................................................................................43
3.16.5. Short Circuit Protection ....................................................................................................44
3.16.6. Thermal Shutdown Registers ...........................................................................................44
4. INPUT AUDIO PROCESSING ................................................................................................. 47
4.1. Analog Inputs ...................................................................................................................................47
4.1.1. Input Registers ...................................................................................................................48
4.2. Mono Mixing and Output Configuration ...........................................................................................48
4.2.1. ADC Registers ...................................................................................................................49
4.3. Microphone Bias ..............................................................................................................................50
4.3.1. Microphone Bias Control Register .....................................................................................50
4.4. Programmable Gain Control ............................................................................................................50
4.4.1. Input PGA Software Control Register. ...............................................................................51
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.6 08/13
ACS422X00
ACS422x00
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
4.5. ADC Digital Filter .............................................................................................................................51
4.5.1. ADC Signal Path Control Register .....................................................................................53
4.5.2. ADC High Pass Filter Enable modes .................................................................................53
4.6. Digital ADC Volume Control .............................................................................................................53
4.6.1. ADC Digital Registers ........................................................................................................54
4.7. Automatic Level Control (ALC) ........................................................................................................54
4.7.1. ALC Operation ..................................................................................................................54
4.7.2. ALC Registers ....................................................................................................................56
4.7.3. Peak Limiter .......................................................................................................................57
4.7.4. Input Threshold ..................................................................................................................57
4.8. Digital Microphone Support .............................................................................................................57
4.8.1. DMIC Register ...................................................................................................................60
5. DIGITAL AUDIO AND CONTROL INTERFACES ................................................................... 61
5.1. Data Interface ..................................................................................................................................61
5.2. Master and Slave Mode Operation ..................................................................................................61
5.3. Audio Data Formats .........................................................................................................................62
5.4. Left Justified Audio Interface ...........................................................................................................62
5.5. Right Justified Audio Interface (assuming n-bit word length) ...........................................................62
5.6. I2S Format Audio Interface ..............................................................................................................63
5.7. Data Interface Registers ..................................................................................................................63
5.7.1. Audio Data Format Control Register ..................................................................................63
5.7.2. Audio Interface Output Tri-state .........................................................................................64
5.7.3. Audio Interface Bit Clock and LR Clock configuration ........................................................64
5.7.4. Bit Clock and LR Clock Mode Selection ............................................................................65
5.7.5. ADC Output Pin State ........................................................................................................66
5.7.6. Audio Interface Control 3 Register .....................................................................................66
5.8. Bit Clock Mode .................................................................................................................................66
5.9. Control Interface ..............................................................................................................................67
5.9.1. Register Write Cycle ..........................................................................................................67
5.9.2. Multiple Write Cycle ...........................................................................................................68
5.9.3. Register Read Cycle ..........................................................................................................68
5.9.4. Multiple Read Cycle ...........................................................................................................69
5.9.5. Device Addressing and Identification .................................................................................69
6. AUDIO CLOCK GENERATION ............................................................................................... 71
6.1. Internal Clock Generation (ACLK) ...................................................................................................71
6.1.1. External MCLK or XTAL .....................................................................................................71
6.1.2. REF Out .............................................................................................................................71
6.2. ACLK Clocking and Sample Rates ..................................................................................................71
6.3. DAC/ADC Modulator Rate Control ...................................................................................................72
7. PLL SECTION ........................................................................................................................ 74
7.1. PLL Block diagram ...........................................................................................................................74
7.2. PLL Defaults ....................................................................................................................................74
7.3. PLL Registers ..................................................................................................................................75
8. CHARACTERISTICS ............................................................................................................... 76
8.1. Electrical Specifications ...................................................................................................................76
8.1.1. Absolute Maximum Ratings ...............................................................................................76
8.1.2. Recommended Operating Conditions ................................................................................76
8.2. Device Characteristics .....................................................................................................................77
8.3. PLL Electrical Characteristics ..........................................................................................................79
9. REGISTER MAP ...................................................................................................................... 80
10. PIN INFORMATION ............................................................................................................... 82
10.1. ACS422A00 Pin Diagram ..............................................................................................................82
10.2. ACS422D00 Pin Diagram ..............................................................................................................83
10.3. Pin Tables ......................................................................................................................................84
10.3.1. Power Pins .......................................................................................................................84
10.3.2. Reference Pins ................................................................................................................84
10.3.3. Analog Input Pins .............................................................................................................85
10.3.4. Analog Output Pins ..........................................................................................................85
10.3.5. Data and Control Pins ......................................................................................................85
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.6 08/13
ACS422X00
ACS422x00
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
10.3.6. PLL Pins ...........................................................................................................................86
11. PACKAGE INFORMATION ................................................................................................... 87
11.1. TAG/TLA Package Drawing ...........................................................................................................87
11.2. Pb Free Process- Package Classification Reflow Temperatures ..................................................87
12. APPLICATION INFORMATION ............................................................................................ 88
13. ORDERING INFORMATION ................................................................................................. 88
14. DISCLAIMER ......................................................................................................................... 88
15. DOCUMENT REVISION HISTORY ....................................................................................... 89
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.6 08/13
ACS422X00
ACS422x00
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
LIST OF FIGURES
Figure 1. Block Diagram ...................................................................................................................................8
Figure 2. Output Audio Processing ................................................................................................................12
Figure 3. Prescaler & EQ Filters ....................................................................................................................15
Figure 4. 6-Tap IIR Equalizer Filter ................................................................................................................15
Figure 5. DAC Coefficient RAM Write Sequence ...........................................................................................17
Figure 6. DAC Coefficient RAM Read Sequence ...........................................................................................18
Figure 7. Gain Compressor, Output vs Input .................................................................................................21
Figure 8. Compressor block diagram .............................................................................................................23
Figure 9. 3-D Channel Inversion ....................................................................................................................29
Figure 10. Bass Enhancement .......................................................................................................................29
Figure 11. Treble Enhancement ....................................................................................................................30
Figure 12. Interpolation and Filtering .............................................................................................................32
Figure 13. Constant Output Power Error ........................................................................................................36
Figure 14. Constant Output Power nominal and high/low ..............................................................................36
Figure 15. Temp sense volume adjustment algorithm ...................................................................................43
Figure 16. Input Audio Processing .................................................................................................................47
Figure 17. Mic Bias ........................................................................................................................................50
Figure 18. ADC Filter Data path .....................................................................................................................51
Figure 19. ADC Input processing ...................................................................................................................52
Figure 20. ALC Operation ..............................................................................................................................54
Figure 21. Single Digital Microphone (data is ported to both left and right channels) ....................................59
Figure 22. Stereo Digital Microphone Configuration ......................................................................................60
Figure 23. Master mode .................................................................................................................................61
Figure 24. Slave mode ...................................................................................................................................61
Figure 25. Left Justified Audio Interface (assuming n-bit word length) ..........................................................62
Figure 26. Right Justified Audio Interface (assuming n-bit word length) ........................................................62
Figure 27. I2S Justified Audio Interface (assuming n-bit word length) ...........................................................63
Figure 28. Bit Clock mode ..............................................................................................................................67
Figure 29. 2-Wire Serial Control Interface ......................................................................................................68
Figure 30. Multiple Write Cycle ......................................................................................................................68
Figure 31. Read Cycle ...................................................................................................................................69
Figure 32. Multiple Read Cycle ......................................................................................................................69
Figure 33. PLL Block Diagram .......................................................................................................................74
Figure 34. ACS422A00 Pinout .......................................................................................................................82
Figure 35. ACS422D00 Pinout .......................................................................................................................83
Figure 36. Package Outline ...........................................................................................................................87
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©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
V1.6 08/13
ACS422X00
