ACT5231
32-Bit Superscaler Microprocessor
Features
s
s
Full militarized QED RM5231 microprocessor
Pinout compatible with popular RM5230 with split power sup
plies (2.5V and 3.3V)
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q
133,
s
High-performance floating point unit
q
532
s
150 and 200 MHz operating frequencies – Consult Factory for
latest speeds
q
325 Dhrystone2.1 MIPS
q
SPECInt95 5.0, SPECfp95 5.25
s
MFLOPS single-precision performance
cycle repeat rate for common single precision opera-tions
and some double precision operations
q
Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q
Single cycle repeat rate for single precision combined multiply-
add operation
q
Single
s
MIPS IV instruction set
q
Floating
System interface optimized for embedded applications
system interface lowers total system cost
performance write protocols maximize uncached write
bandwidth with 600 MB per second peak throughput
q
Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9
q
IEEE 1149.1 JTAG boundary scan
q
High
q
32-bit
point multiply-add instruction increases performance in
signal processing and graphics applications
q
Conditional moves to reduce branch frequency
q
Index address modes (register + register)
s
Embedded application enhancements
DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
q
I and D cache locking by set
q
Optional dedicated exception vector for interrupts
q
Specialized
s
Integrated on-chip caches
instruction and 32KB data - 2 way set associative and per
set locking
q
Virtually indexed, physically tagged
q
Write-back and write-through on per page basis
q
Pipeline restart on first double for data cache misses
q
32KB
s
Fully static CMOS design with power down logic
q
Standby
reduced power mode with WAIT instruction
q
2.7 W typical power @ 200MHz
q
2.5V core with 3.3V IO’s
s
s
Integrated memory management unit
q
Fully
associative joint TLB (shared by I and D translations)
q
48 dual entries map 96 pages
q
Variable page size (4KB to 16MB in 4x increments)
128-pin Power Quad-4 package (F22),
Consult Factory for
package configuration
Block Diagram
Preliminary
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5231 REV 1 12/22/98
DESCRIPTION
The ACT5231 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 32KB
2-way set associative instruction cache, a 32KB
2-way set associative data cache, and an efficient
32-bit system interface. The ACT5231 can issue
both an integer and a floating point instruction in the
same cycle.
The ACT5231 is ideally suited for high-end
embedded
control
applications
such
as
internetworking,
high
performance
image
manipulation, high speed printing, and 3-D
visualization.
Integer Unit
The ACT5231 implements the MIPS IV
Instruction Set Architecture, and is therefore fully
upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the
ACT5231 includes two implementation specific
instructions not found in the baseline MIPS IV ISA
but that are useful in the embedded market place.
Described in detail in the QED RM5231 datasheet,
these instructions are integer multiply-accumulate
and 3-operand integer multiply.
The ACT5231 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer multiply/divide operations, and the program
counter(PC).
HARDWARE OVERVIEW
The ACT5231 offers a high-level of integration
targeted
at
high-performance
embedded
applications. The key elements of the ACT5231 are
briefly described below.
Register File
The ACT5231 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registersich allo are used for scalar integer
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
Superscalar Dispatch
The ACT5231 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-add, converts, etc. In combination with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT5231 provides unparalleled price/performance
in
computationally
intensive
embedded
applications.
ALU
The ACT5231 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perform all tions
in a single processor cycle.
CPU Registers
Like all MIPS ISA processors, the ACT5231 CPU
has a simple, clean user visible state consisting of
32 general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark™ RM 5231™, 32-Bit Superscalar
Microprocessor see the latest QED datasheet.
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5231 uses
the simple 5-stage pipeline also found in the
ACT52xx family, R4600, R4700, and R5000. In
addition to this standard pipeline, the ACT5231
uses an extended seven stage pipeline for
floating-point operations. The ACT5231 does
virtual to physical translation in parallel with cache
access.
Aeroflex Circuit Technology
2
SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700
ACT5231 Microprocessor PQUAD Pinouts
(Pinouts subject to change – Contact Factory)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Aeroflex Circuit Technology
Function
Vcc
NC
NC
Vcc
Vss
SysAD4
SysAD36
SysAD5
SysAD37
Vcc†
Vss
SysAD6
SysAD38
Vcc
Vss
SysAD7
SysAD39
SysAD8
SysAD40
Vcc†
Vss
SysAD9
SysAD41
Vcc
Vss
SysAD10
SysAD42
SysAD11
SysAD43
Vcc†
Vss
SysAD12
SysAD44
Vcc
Vss
SysAD13
SysAD45
SysAD14
SysAD46
Vcc†
Vss
SysAD15
SysAD47
Vcc
Vss
ModeClock
JTDO
JTDI
JTCK
JTMS
Vcc
Vss
e&
g
ka
c
Pa
(
Pin #
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
uts
ino
P
Function
NC
NC
NC
Vcc
Vss
ModeIn
RdRdy*
WrRdy*
ValidIn*
ValidOut*
Release*
VccP
VssP
SysClock
Vcc†
Vss
Vcc
Vss
Vcc†
Vss
SysCmd0
SysCmd1
SysCmd2
SysCmd3
Vcc
Vss
SysCmd4
SysCmd5
Vcc
Vss
SysCmd6
SysCmd7
SysCmd8
SysCmdP
Vcc†
Vss
Vcc†
Vss
Vcc
Vss
Int0*
Int1*
Int2*
Int3*
Int4*
Int5*
Vcc
Vss
NC
NC
NC
NC
tt
jec
ub
s
Pin #
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
e–
g
an
ch
o
Function
Vcc
NMI*
ExtRqst*
Reset*
ColdReset*
VccOK
BigEndian
Vcc
Vss
SysAD16
SysAD48
Vcc†
Vss
SysAD17
SysAD49
SysAD18
SysAD50
Vcc
Vss
SysAD19
SysAD51
Vcc†
Vss
SysAD20
SysAD52
SysAD21
SysAD53
Vcc
Vss
SysAD22
SysAD54
Vcc†
Vss
SysAD23
SysAD55
SysAD24
SysAD56
Vcc
Vss
SysAD25
SysAD57
Vcc†
Vss
SysAD26
SysAD58
SysAD27
SysAD59
Vcc
Vss
NC
NC
Vss
)
ry
cto
a
tF
ta c
on
C
Pin #
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Function
NC
NC
NC
NC
Vcc
Vss
SysAD28
SysAD60
SysAD29
SysAD61
Vcc†
Vss
SysAD30
SysAD62
Vcc
Vss
SysAD31
SysAD63
SysADC2
SysADC6
Vcc†
Vss
SysADC3
SysADC7
Vcc
Vss
SysADC0
SysADC4
Vcc†
Vss
SysADC1
SysADC5
SysAD0
SysAD32
Vcc
Vss
SysAD1
SysAD33
Vcc†
Vss
SysAD2
SysAD34
SysAD3
SysAD35
Vcc
Vss
NC
NC
NC
NC
Vcc
Vss
† These V
CC
pins may be 2.5V in future higher performance devices
3
SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Sample Ordering Information
Part Number
ACT-5231PC-133F22C
ACT-5231PC-150F22T
ACT-5231PC-200F22M
Screening
Commercial Temperature
Military Temperature
Military Screening
Speed (MHz)
133
150
200
Package
128 Lead PQUAD
128 Lead PQUAD
128 Lead PQUAD
Part Number Breakdown
ACT– 5231 PC – 200 F22 M
Aeroflex Circuit
Technology
Base Processor Type
Cache Style
PC = Primary Cache
Screening
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened
*
Q = MIL-PRF-38534 Compliant/SMD if applicable
Package Type & Size
Maximum Pipeline Freq.
133 = 150MHz
150 = 150MHz
200 = 200MHz
Surface Mount Package
F22 = 1.10" SQ 128 Lead PQUAD
*
Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
www.aeroflex.com/act1.htm
Aeroflex Circuit Technology
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: (800) 843-1553
E-Mail: sales-act@aeroflex.com
4
SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700
FPGA/CPLD
