a
FEATURES
Complete Monolithic 12-Bit 10 s Sampling ADC
On-Board Sample-and-Hold Amplifier
Industry Standard Pinout
8- and 16-Bit Microprocessor Interface
AC and DC Specified and Tested
Unipolar and Bipolar Inputs
5 V, 10 V, 0 V–10 V, 0 V–20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 and SMD Compliant Versions Available
12/8
CS
A
0
CE
R/C
REF OUT
10V
REF
CLOCK
12-Bit 100 kSPS
A/D Converter
AD1674*
FUNCTIONAL BLOCK DIAGRAM
STS
REGISTERS / 3-STATE OUTPUT BUFFERS
CONTROL
SAR
12
AGND
20k
REF IN
5k
BIP OFF
20V
IN
COMP
10k
10k
IDAC
12
12
DB11 (MSB)
DB0 (LSB)
5k
2.5k
2.5k
SHA
DAC
10V
IN
5k
AD1674
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD1674 is a complete, multipurpose, 12-bit analog-to-
digital converter, consisting of a user-transparent onboard
sample-and-hold amplifier (SHA), 10 volt reference, clock and
three-state output buffers for microprocessor interface.
The AD1674 is pin compatible with the industry standard
AD574A and AD674A, but includes a sampling function while
delivering a faster conversion rate. The on-chip SHA has a wide
input bandwidth supporting 12-bit accuracy over the full
Nyquist bandwidth of the converter.
The AD1674 is fully specified for ac parameters (such as S/(N+D)
ratio, THD, and IMD) and dc parameters (offset, full-scale
error, etc.). With both ac and dc specifications, the AD1674 is
ideal for use in signal processing and traditional dc measure-
ment applications.
The AD1674 design is implemented using Analog Devices’
BiMOS II process allowing high performance bipolar analog cir-
cuitry to be combined on the same die with digital CMOS logic.
Five different temperature grades are available. The AD1674J
and K grades are specified for operation over the 0°C to +70°C
temperature range. The A and B grades are specified from
–40°C to +85°C; the AD1674T grade is specified from –55°C
to +125°C. The J and K grades are available in both 28-lead
plastic DIP and SOIC. The A and B grade devices are available
in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC.
The T grade is available in 28-lead hermetically sealed ceramic
DIP.
*Protected
by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586
.
1. Industry Standard Pinout: The AD1674 utilizes the pinout
established by the industry standard AD574A and AD674A.
2. Integrated SHA: The AD1674 has an integrated SHA which
supports the full Nyquist bandwidth of the converter. The
SHA function is transparent to the user; no wait-states are
needed for SHA acquisition.
3. DC and AC Specified: In addition to traditional dc specifica-
tions, the AD1674 is also fully specified for frequency do-
main ac parameters such as total harmonic distortion,
signal-to-noise ratio and input bandwidth. These parameters
can be tested and guaranteed as a result of the onboard
SHA.
4. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges:
0 V to +10 V and 0 V to +20 V unipolar, –5 V to +5 V and
–10 V to +10 V bipolar. The AD1674 operates on +5 V and
±
12 V or
±
15 V power supplies.
5. Flexible Digital Interface: On-chip multiple-mode
three-state output buffers and interface logic allow direct
connection to most microprocessors.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD1674–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
INTEGRAL NONLINEARITY (INL)
DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)
UNIPOLAR OFFSET
1
@ +25°C
BIPOLAR OFFSET
1
@ +25°C
FULL-SCALE ERROR
1, 2
@ +25°C
(with Fixed 50
Ω
Resistor from REF OUT to REF IN)
TEMPERATURE RANGE
TEMPERATURE DRIFT
3
Unipolar Offset
2
Bipolar Offset
2
Full-Scale Error
2
POWER SUPPLY REJECTION
V
CC
= 15 V
±
1.5 V or 12 V
±
0.6 V
V
LOGIC
= 5 V
±
0.5 V
V
EE
= –15 V
±
1.5 V or –12 V
±
0.6 V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
V
LOGIC
V
CC
V
EE
Operating Current
I
LOGIC
I
CC
I
EE
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads)
4
(External Load Should Not Change During Conversion
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25°C value to the value at T
MIN
or T
MAX
.
4
Reference should be buffered for
±
12 V operation.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, V
CC
= +15 V 10% or +12 V
–12 V 5% unless otherwise noted)
5%, V
LOGIC
= +5 V
10%, V
EE
= –15 V
10% or
AD1674J
Min
Typ
12
Max
Min
12
AD1674K
Typ
Max
Unit
Bits
±
1
±
1/2
LSB
12
±
3
±
6
0.1
0
0.25
+70
±
2
±
2
±
6
±
2
±
1/2
±
2
12
±
2
±
4
0.1
0
0.25
+70
±
1
±
1
±
3
±
1
±
1/2
±
1
Bits
LSB
LSB
% of FSR
°C
LSB
LSB
LSB
LSB
LSB
LSB
–5
–10
0
0
3
6
5
10
+5
+10
+10
+20
7
14
–5
–10
0
0
3
6
5
10
+5
+10
+10
+20
7
14
Volts
Volts
Volts
Volts
kΩ
kΩ
+4.5
+11.4
–16.5
5
10
14
385
9.9
10.0
+5.5
+16.5
–11.4
8
14
18
575
10.1
2.0
+4.5
+11.4
–16.5
5
10
14
385
9.9
10.0
+5.5
+16.5
–11.4
8
14
18
575
10.1
2.0
Volts
Volts
Volts
mA
mA
mA
mW
Volts
mA
–2–
REV. C
AD1674
AD1674A
Min Typ Max
12
±
1
±
1
12
±
2
±
6
0.1
–40
0.25
+85
±
2
±
2
±
8
±
2
±
1/2
±
2
–40
0.1
12
±
2
±
3
0.125
+85
±
1
±
1
±
5
±
1
±
1/2
±
1
–55
0.1
AD1674B
Min Typ Max
12
±
1/2
±
1/2
12
±
2
±
3
0.125
+125
±
1
±
2
±
7
±
1
±
1/2
±
1
AD1674T
Min Typ Max
12
±
1/2
±
1
Parameter
RESOLUTION
INTEGRAL NONLINEARITY (INL)
DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)
UNIPOLAR OFFSET
1
@ +25°C
BIPOLAR OFFSET
1
@ +25°C
FULL-SCALE ERROR
1, 2
@ +25°C
(with Fixed 50
Ω
Resistor from REF OUT to REF IN)
TEMPERATURE RANGE
TEMPERATURE DRIFT
3
Unipolar Offset
2
Bipolar Offset
2
Full-Scale Error
2
POWER SUPPLY REJECTION
V
CC
= 15 V
±
1.5 V or 12 V
±
0.6 V
V
LOGIC
= 5 V
±
0.5 V
V
EE
= –15 V
±
1.5 V or –12 V
±
0.6 V
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
V
LOGIC
V
CC
V
EE
Operating Current
I
LOGIC
I
CC
I
EE
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads)
4
(External Load Should Not Change During Conversion
Unit
Bits
LSB
LSB
Bits
LSB
LSB
% of FSR
°C
LSB
LSB
LSB
LSB
LSB
LSB
–5
–10
0
0
3
6
5
10
+5
+10
+10
+20
7
14
–5
–10
0
0
3
6
5
10
+5
+10
+10
+20
7
14
–5
–10
0
0
3
6
5
10
+5
+10
+10
+20
7
14
Volts
Volts
Volts
Volts
kΩ
kΩ
+4.5
+11.4
–16.5
5
10
14
385
9.9
10.0
+5.5 +4.5
+16.5 +11.4
–11.4 –16.5
8
14
18
575
10.1
2.0
9.9
5
10
14
385
10.0
+5.5 +4.5
+16.5 +11.4
–11.4 –16.5
8
14
18
575
10.1
2.0
9.9
5
10
14
385
10.0
+5.5
+16.5
–11.4
8
14
18
575
10.1
2.0
Volts
Volts
Volts
mA
mA
mA
mW
Volts
mA
REV. C
–3–
AD1674–SPECIFICATIONS
AC SPECIFICATIONS
Parameter
Signal to Noise and Distortion (S/N+D) Ratio
2, 3
Total Harmonic Distortion (THD)
4
Peak Spurious or Peak Harmonic Component
Full Power Bandwidth
Full Linear Bandwidth
Intermodulation Distortion (IMD)
5
Second Order Products
Third Order Products
SHA (Specifications are Included in Overall Timing Specifications)
Aperture Delay
Aperture Jitter
Acquisition Time
(T
MIN
to T
MAX
, with V
CC
= +15 V 10% or +12 V 5%, V
LOGIC
= +5 V 10%, V
EE
= –15 V 10% or
–12 V 5%, f
SAMPLE
= 100 kSPS, f
IN
= 10 kHz, stand-alone mode unless otherwise noted)
1
AD1674J/A
Min
Typ
Max
69
70
–90
–92
1
500
–90
–90
50
250
1
–80
–80
–82
0.008
–82
1
500
–90
–90
50
250
1
–80
–80
AD1674K/B/T
Min
Typ
Max
70
71
–90
–92
–82
0.008
–82
Units
dB
dB
%
dB
MHz
kHz
dB
dB
ns
ps
µs
DIGITAL SPECIFICATIONS
Parameter
(for all grades T
MIN
to T
MAX
, with V
CC
= +15 V
V
EE
= –15 V 10% or –12 V 5%)
Test Conditions
10% or +12 V
Min
+2.0
–0.5
–10
–10
5%, V
LOGIC
= +5 V
Max
V
LOGIC
+0.5 V
+0.8
+10
+10
10
10%,
Units
V
V
µA
µA
pF
V
V
µA
pF
LOGIC INPUTS
V
IH
High Level Input Voltage
V
IL
Low Level Input Voltage
I
IH
High Level Input Current (V
IN
= 5 V)
I
IL
Low Level Input Current (V
IN
= 0 V)
C
IN
Input Capacitance
LOGIC OUTPUTS
V
OH
High Level Output Voltage
V
OL
Low Level Output Voltage
I
OZ
High-Z Leakage Current
C
OZ
High-Z Output Capacitance
V
IN
= V
LOGIC
V
IN
= 0 V
I
OH
= 0.5 mA
I
OL
= 1.6 mA
V
IN
= 0 to V
LOGIC
+2.4
–10
+0.4
+10
10
NOTES
1
f
IN
amplitude = –0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to –0 dB (9.997 V p-p) input signal unless
otherwise noted.
2
Specified at worst case temperatures and supplies after one minute warm-up.
3
See Figures 12 and 13 for other input frequencies and amplitudes.
4
See Figure 11.
5
fa = 9.08 kHz, fb = 9.58 kHz with f
SAMPLE
= 100 kHz. See
Definition of Specifications
section and Figure 15.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–4–
REV. C
AD1674
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
Parameter
Conversion Time
8-Bit Cycle
12-Bit Cycle
STS Delay from CE
CE Pulse Width
CS
to CE Setup
CS
Low During CE High
R/C to CE Setup
R/C Low During CE High
A
0
to CE Setup
A
0
Valid During CE High
J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
t
C
t
C
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
7
9
50
50
50
50
50
0
50
8
10
200
50
50
50
50
50
0
50
7
9
8
µs
10
µs
225 ns
ns
ns
ns
ns
ns
ns
ns
t
HEC
t
HSC
t
SSC
t
SRC
t
HRC
(for all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= –15 V 10% or –12 V 5%; V
IL
= 0.4 V,
V
IH
= 2.4 V unless otherwise noted)
CE
__
CS
_
R/C
A
0
t
SAC
t
HAC
t
C
STS
DB11 – DB0
t
DSC
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
Access Time
Data Valid After CE Low
Output Float Delay
CS
to CE Setup
R/C to CE Setup
A
0
to CE Setup
CS
Valid After CE Low
R/C High After CE Low
A
0
Valid After CE Low
J, K, A, B, Grades
T Grade
Symbol Min Typ Max Min Typ Max Units
t
DD1
t
HD
t
HL5
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
75
25
2
20
3
150
50
0
50
0
0
50
50
0
50
0
0
50
150
25
2
15
4
75
150 ns
ns
ns
150 ns
ns
ns
ns
ns
ns
ns
HIGH IMPEDANCE
Figure 1. Converter Start Timing
CE
__
CS
t
SSR
_
R/C
t
HSR
t
SSR
t
HRR
A
0
t
SAR
t
HS
NOTES
1
t
DD
is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0°C to T
MAX
.
3
At –40°C.
4
At –55°C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
t
HAR
STS
t
HD
DB11 – DB0
HIGH
IMPEDANCE
DATA
VALID
HIGH
IMP.
t
DD
t
HL
Figure 2. Read Timing
Test
Access Time High Z to Logic Low
Float Time Logic High to High Z
Access Time High Z to Logic High
Float Time Logic Low to High Z
V
CP
5V
0V
0V
5V
C
OUT
100 pF
10 pF
100 pF
10 pF
D
OUT
C
OUT
I
OL
V
CP
I
OH
Figure 3. Load Circuit for Bus Timing Specifications
REV. C
–5–
微控制器 MCU
