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ANALOG DEVICES fAX-ON-DEHAND HOTLINE

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-..

ANALOG

DEVICES

FEATURES

1.3 Arc Minute Accuracy

16-81t Resolution

Small 28-Pin Ceramic DIP

Low Cost

APPLICATIONS

Gimbal/Gyro Control Systems

Radar System

Engine Controllers

Sonar

Military Servo Control Systems

Fire Control Systems

Avionic Systems

Antenna Monitoring

CNC Machine Tooling

LowCost, 6-BitSynchro/

Resolver

-to-Digital

Converter

AD2S46

The device incorporates a high accuracy differential conditioning

circuit for signal inputs providing more than 74 dB of common-

mode rejection. Options are available for both synchro and re-

solver format inputs. The convener outpUt is via a tristate

transparent latch allmving data to be read without interruprion

of converter operation.

Digital data transfer is accommodated by an ENABLE input

which controls the tristate outpUts and presents the data to the

bus when taking from a HI to a LO statc.

An INHIBIT precedes the ENABLE inpUt and freezes the data

transfer from the up-down counter to the oUtput latches. This

action does not interrupt the operation of the tracking loop. Re-

leasing the HI/HIBIT aUtomatical1ygenerates a data refresh. A

BYTE SELECT input provides the facility for interfacing to an

8- or 16-bit bus system.

OBS

RHO

Rla

GENERAL DESCRIPTION

The AD2S46 series are 16-bit, continuous tracking synchrol

resolver-to-digital conveners. They have been designed specifi-

cally for applicarions where space and performance are al a pre-

mium. Each 28-pin hybrid device uses a Type 2 servo loop

tracking converter with a ratiometTic conversion technique to

provide excellent noise immunity, repeatability and tolerance of

long lead lengths.

The core of each conversion is performed by a state of the art

monolithic integrated circuit manufactured in Analog Devices'

proprietary BiMOS II process which combines the advantage of

low power CMOS digital logic with bipolar linear circuits. The

use of these ICs keeps the internal component count low provid-

ing both packaging which reflects LSI monolithic standards and

ensures high reliability.

FUNCTIONAL

REFERENCE

CONDITIONER

REF

OLE

MODELS AVAILABLE

The AD2S46 series is available in 2 accuracy grades;

AD2S46TD 16 Bits:!: 1.3 arc mins -55°C to .t 125cC

AD2S46SD 16 Bits :t 2.6 arc mim - 55°C to T 125°C

Each grade has options available which wiIJ interface to standard

synchros and resolvers.

BLOCK DIAGRAM

-vs

+Vs

GND

AD2S46

PHASE

SENSITIVE

DETECTOR

INTEGRA TOR

UP/DOWN

COUNTER

All components are 100% tested at

-.-

55°C, + 25°C, and -+- 2SoC.

Devices processed to high reliability screening standards (Suftix

B) receive further levels of testing and screening to ensure high

levels of reliability. Full ordering information is given on the

back page of this data sheet.

RESOLVERI

SYNCHRO

CONDITIONER

HIGH

DYNAMIC

RANGE VCO

BYTE

SELECT

ENAiiLE

Signature

INHIBIT

REV. 0

DB1 TO DB16

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use; nor for any infringements of patents Drother rights of third parties

which may result from its use. No license is granted by implication Dr

otherwise under any patent or patent rights of Analog

Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax:

617/326-8703

Twx; 710/394-6577

Telex: 924491

Cable:

ANALOG NORWOODMASS

ANALOGDEVICES fAX-ON-DEHAND HOTLINE

Page

AD2S46

-SPECIFICATIONS

at +25°&unlessspecifiedotherwise)

(typical

Parameter

PERFORMANCE

Accuracyt

AD2S46TD

AD2S46SD

Tracking Rate

Resolution

Repeatability

Signal/Referenee

Frequency

Bandwidth

SIGNAL INPUTS

Signal Voltage

Impedance

90 V Signal

26 V Signal

11.8 V Signal

2 V Signal

Common-Mode Rejection

Common-Mode Range

90 V Signal

26 V Signal

11.8 V Signal

2 V Signal

REFERENCE INPUTS

Reference Voltage

Impedance

115 V Reference

26 V Reference

11.8 V Reference

2 V Reference

Common-Mode Range

115 V Reference

26 V Reference

11.8 V Reference

2 V Reference

INHIBIT

Sense

Time to Stable Data (After

Negative Edge of Inhibit)

ENABLE

Logic LO to Data Available

Logic HI to High Impedance

BYTE SELECT

Logic HI to Data Stable

Logic LO to Data Stable

STEP RESPONSE

Large Stept

Small Slept

ACCELERATION

CONSTANT

BYTE SELECT)

0.8

2.0

:!:100

:!:lOO

Vdc

.....A

48000

DIGITAL INPUTS

(ENABLE, INHIBIT,

V[L

V[H

In,

IJH

MiD

AD2S46

Typ

Max

Units

ClJmments

:t:1.3

:t:2.6

(1 LSB = 20 arc see)

360

2860

2, 11.8,26, 90 :t 10%

200

4.4

arc min

levis

Bits

LSB

Vrms

Parallel Natural Binary

1 IN65356

See Ordering Information

Resistive Tolerance:!: 2%

OBS

OLE

=250

:t 120

=60

:t 12

Vde

Vdc

V de

Vde

2, 11.8,26, 115 :!:10%

275

V rmg

See Ordering Information

Resistive Tolerance:!: 5%

:!:210

=35

:!:3S

Vdc

See Figure 3

Logic LO to Inhibit

600

110

130

140

illS

See Figure 3

Presents Data to OutpUt

Outputs in High Impedance State

See Figure 3

MS Byte DBI-DB8

LS Byte DBI-DB8

1790 to 1 LSB of Error

ZOto 1 LSB of Error

see 2

VIL

VJH

= 0V

-2-

REV.0

ANALOGDEVICES fAX-ON-DEMAND HOTLINE

Page 1~

AD2S46

Comments

IOL

IoH

Parameter

MiD

AD2S46

Typ

Max

0.4

Units

V dc

DIGITAL OUTPUTS (DBI-DB16)

VOLI

VORl

2.4

:tl00

Tristate Leakage CUlTent

Drive Capability

POWER SUPPLIES

Voltage Levels

+VSI

-VSI

Current

+Is

-Is

V de

j..lA

LSTIL

1.2 mA

100 j..lA

+ 14.25

-14.25

+15

-IS

+ 15.75

-IS.75

Vde

OBS

WEIGHT

NOTES

Specifications subject to change without notice.

Power Dissipation

DIMENSIONS

675

1.4 x 0.6 x 0.135

35.6 x 15.2 x 3.4

825

inch

See Package Information

0.25

6.3

Grams

'Specified over temperature range, -SS.C to H2S.C, and for: (a) :!:IO% signal and reference amplitUde variation; (b) :<::10%signal :<:: nd reference harmonic

distonion; (c) ",5% power supply variation; (d) :;:10% variation in reference frequency.

Boldface type indicates parameters which are 100% tested at nominal values of power supplies, input signal voltages, and operating frequency. Ail otHer

parameters are guaranteed by design, not tested.

ABSOLUTE MAXIMUM RATINGS

+VstoGND

-VstoGND

Any Logic Input to GND (max)

"""""'"

Any Logie Input to GND (min)

SI, 82, 83, 84 (Line to Line)l

(90 V Option)

(26VOption)

(l1.8VOption)

(2 V Option)

Sl, S2, 83, S4 to GND

(90 V Option)

(26VOprion)

(11.8 V Option)

(2 V Option)

RHI to RLo

(26V,115VOptions)

(2 V, 11.8 V Options)

RHI and RLo to GND

(26 V, l1SVOptions)

(2V,11.8VOptions)

Storage Temperature

Range.

MaximumJunction Temperature. . . . . . . . . . . . . . . .

OLE

+17.25Vdc

17.2SVdc

+5.5 V de

-0.4 V de

IS0aC

NOTE

JOn synchro inpUt options, line to line voltage refers to the S2-SI, SI-53

and 53-S2 differential voltages. On resolver input options line to Hne Levels

refer to the SI-53 and S2-54 voltages.

'Thermal Resistance: To ensure that the junction temperatUre of the hottest

cOmponent within rhe hybrid does not exceed the rated maximum of 150.C,

the case temperature must not exceed 130.C.

:t600Vdc

:t160Vdc

::t:80Vdc

::t:14Vdc

::t:250Vdc

::t:120Vdc

:t60Vdc

:t12Vdc

::t:600Vdc

::t50Vdc

:!:21OVdc

:!:35Vdc

. . . . . . . . . . . -65aC

Isoac

OperatingTemperature Range2

-S5°C to + 12SoC

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+Vs to GND)

+15 V dc ::t5%

PowerSupplyVoltage(-VstoGND)

-15Vdc :!:S%

Analog Input Voltage (51,

52, 53,

S4 Line to Line)

(90VOption)

90Vrms::tIO%

(26VOption)

26Vrms::tIO%

(l1.8VOption)

11.8VrIDs:dO%

(2 V Option)

2Vrms:t10%

Analog Input Voltage (RHI to RLo)

26Vrms::tIO%

(26 V Option)

(115 V Option)

1l5Vrms::tlO%

(11.8 V Option)

11.8Vrms:!:10%

(2 V Option)

2Vrms:!:10%

Signal and Reference Harmonic Distortion.

. . . . . . . . :!:10%

Phase Shift Between Signal and Reference.

. . .

:!:

10 Degrees

Ambient Operating Temperature Range. . . . - 55°C to + 125°C

CAUTION

1. Absolute maximum ratings are the limits beyond which dam-

age to the device may occur.

ESD SENSITIVITY

The AD2S46 features input protection circuitry consisting of large "distributed" diodes and

polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,

low energy pulses (Charged Device Model).

2. Correct polarity voltages must be maintained on the + Vs and

-Vs pins.

WARNIN

Proper ESD precautions are strongly recommended to avoid functional damage or performance

degradation. For further information on ESD precautions, refer to Analog Devices'

ESD Preven-

tion Manual.

REV. 0

0 SfNSIT lYE DEVICf

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RNRLOGDEVICES fRX-ON-DEHRND HOTLINE

Page

AD2S46

PIN CONFIGURATION

1--8

21-28

11-14

AD2S46 PIN FUNCTION

MNEMONIC

DB9-DB16

DB1-DB8

ENABLE

BYTE SELECT

S4-S1

RHI

RLo

GND

-Va

+Vs

INHIBIT

DESCRIPTION

PARALLEL OUTPUT DATA BITS

OUTPUT ENABLE INPUT

BYTE SELECT INPUT SIGNAL

SYNCHRO/RESOLVER SIGNAL INPUTS

INPUT PIN FOR REFERENCE HIGH

INPUT PIN FOR REFERENCE LOW

POWER SUPPLY GROUND

NEGATIVE POWER SUPPLY

POSITIVE POWER SUPPLY

INPUT PIN TO INHIBIT CONVERTER

AD2S46

TOPVIEW

(LSa)

BIT 16

L.!

(Not to Scale)

ENABLE

PRINCIPLES OF OPERATION

The AD2S46"series operate on a Type 2 tracking closed-loop

principle. The output digital word continually tracks the posi-

tion of the resolver/synchro shaft without the need for external

convert commands and wait states. As the transducer moves

through a position equivalent to the least significant bit weight-

ing, the oUtput digital word is updated by one LSB.

OBS

Roo

RlO

If the device is a synchro-to-digital converter, the 3-wire synchro

output will be connected to Sl, 52 and 53 on the unit and a

solid-state 5cott-T inpUt conditioner will convert these signals

inro resolver format, i.e.,

VI = K Eo sin UItsin e

(sin)

V 2

K Eo sin wt cas H

(cos)

Where e is the angle of the synchro shaft, Eo sin <utis the refer-

ence signal, and K is the transformation ratio of the input signal

conditioner. If the unit is a resolver-to digital converter, the 4-

wire resolver output will be connected direcdy to SI, S2, 53 and

54 on the unit.

OLE

To understand the conversion process, assume that the current

word state of the up-down counter is <j).V I is multiplied by

cos

<I>

and V2 is multiplied by sin <I> give:

K Eo sin UIt sin e .:os <I>

K Eo sin wt cos e sin <I>

These signals are subtracted

by the error amplifier

cos fI sin <1»

to give:

K Eo sin wt (sin e cos <!>

K Eo sin wt sin (6-<1»

A phase sensitive detector, integrator and voltage controlled os.

cillator (VCO) form a closed-loop system which seeks to null sin

(8-(!». When this is accomplished, the word state of the up-

down counter, (j), equals, to within the rated accuracy of the

converter, the synchro/resolver shaft angle, e.

REFERENCE

CONDITIONER

REF

AD2S46

1..:2

I V2

-vs

+vs

GND

RESOLVERI

SYNCHRO

CONDmONER

BYTE

SELECT

ENABLE

OBI TO DB16

INHIBIT

AD2S46 Functional Block Diagram

-4-

REV. 0

ANALOG DEVICES fAX-ON-DEMAND HOTLINE

Page

AD2S46

OPTIONAL

PHASE SHIFT CIRCUITS

~AAE

PHASELAG= ARCTAN

,t~N

o--f

>. me

2" IRC

OUTPUT

DATA

BYTE

OUTPUT

DATA

MS BYTE

AD2S46

OBS

Es I-S3

ERLO-RHI wt sin e

sin

E53.52

ERLO-RHIsin wt sin (6 -+-120°)

E52-51 = ERLO..RHI in wt sin (0 + 240°)

+15V

CONNECTING THE CONVERTER

The power supply voltages connected to -Y sand + Vspins

should be -15 Yand + 15 Y and must nor be reversed.

OLE

-15V

100k

100nF

PHASE

LEAD!

LAG

OSCILLATOR

(E.G., ose 1758)

Figure

Connection

Diagram

It is suggested that a parallel combination of a 100 nF (ceramic)

and a 6.8 fLF(tantalum) capacitor be placed from each of the

supply pins to GND.

The digital output is taken from Pins 21-28 and Pins 1-8.

Pin 21 is the MSB, Pin 8 the L5B.

The reference connections are made to REF HI and REF LO.

In the case of a synchro, the signals are connected to $1, 52 and

53 according to the following convention:

DATA TRANSFER

To transfer data the i"NH1BIT input should be used. The data

will be valid 600 liS after the application of a logic "LO" to

INHIBIT. By using the ENABLE inpUt the two bytes of data

can be transferred after which the INHIBIT should be retUrned

to a logic "HI" Slate to enable the oUtpUtlarches to be updated.

INHIBIT INPUT

The INHIBIT logic input only inhibits the data transfer from

the up-down coumer to the outpUt latches and, therefore, does

not interrupt the operation of the tracking loop. Releasing the

INHIBIT aUtomatically generates a refresh of the output data.

ENABLE INPUT

The ENABLE input determines rhe state of the omput data. A

logic "HI" maintains the OUtpUtdata pins in the high imped-

ance state, and application of a logic "LO" presents the data of

the latches to the outpUt pins. The operation of the ENABLE

has no effect on the conversion process. Timing information is

shown in Figure 2.

For a resolver, the signals are connected to 51, 52, 53 and 54

according to the following convention:

ESJ-S3 "" ERLORHI

E52-54

sin wt sin

ERLO-RHI sin

wt cos

It is recommended that the resolver is connected using individu-

ally screened twisted pair cables with the sine, cosine and refer-

ence signals twisted separately.

REV. 0

-5-

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