Changes to Table 10 ........................................................................ 22
10/12—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5121
AD5121/AD5141
V
DD
= 2.3 V to 5.5 V, V
SS
= 0 V; V
DD
= 2.25 V to 2.75 V, V
SS
= −2.25 V to −2.75 V; V
LOGIC
= 1.8 V to 5.5 V, −40°C < T
A
< +125°C, unless
otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity
2
Symbol
Test Conditions/Comments
Min
Typ
1
Max
Unit
N
R-INL
7
R
AB
= 10 kΩ
V
DD
≥ 2.7 V
V
DD
< 2.7 V
R
AB
= 100 kΩ
V
DD
≥ 2.7 V
V
DD
< 2.7 V
−1
−2.5
−0.5
−1
−0.5
−8
±0.1
±1
±0.1
±0.25
±0.1
±1
35
55
130
40
60
+1
+2.5
+0.5
+1
+0.5
+8
Bits
LSB
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
Ω
Ω
Resistor Differential Nonlinearity
2
Nominal Resistor Tolerance
Resistance Temperature Coefficient
3
Wiper Resistance
3
R-DNL
ΔR
AB
/R
AB
(ΔR
AB
/R
AB
)/ΔT × 10
6
R
W
Code = full scale
Code = zero scale
R
AB
= 10 kΩ
R
AB
= 100 kΩ
R
AB
= 10 kΩ
R
AB
= 100 kΩ
125
400
80
230
Bottom Scale or Top Scale
R
BS
or R
TS
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity
4
INL
R
AB
= 10 kΩ
R
AB
= 100 kΩ
−0.5
−0.25
−0.25
−1.5
−0.5
±0.1
±0.1
±0.1
−0.1
±0.1
1
0.25
±5
+0.5
+0.25
+0.25
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
Differential Nonlinearity
4
Full-Scale Error
DNL
V
WFSE
R
AB
= 10 kΩ
R
AB
= 100 kΩ
+0.5
1.5
0.5
Zero-Scale Error
V
WZSE
R
AB
= 10 kΩ
R
AB
= 100 kΩ
Code = half scale
Voltage Divider Temperature
Coefficient
3
(ΔV
W
/V
W
)/ΔT × 10
6
Rev. A | Page 3 of 32
AD5121/AD5141
Parameter
RESISTOR TERMINALS
Maximum Continuous Current
Symbol
I
A
, I
B
, and I
W
R
AB
= 10 kΩ
R
AB
= 100 kΩ
Terminal Voltage Range
5
Capacitance A, Capacitance B
3
C
A
, C
B
f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ
R
AB
= 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
R
AB
= 10 kΩ
R
AB
= 100 kΩ
V
A
= V
W
= V
B
−6
−1.5
V
SS
Test Conditions/Comments
Min
Typ
1
Data Sheet
Max
Unit
+6
+1.5
V
DD
mA
mA
V
25
12
pF
pF
Capacitance W
3
C
W
Common-Mode Leakage Current
3
DIGITAL INPUTS
Input Logic
3
High
Low
Input Hysteresis
3
Input Current
3
Input Capacitance
3
DIGITAL OUTPUTS
Output High Voltage
3
Output Low Voltage
3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Logic Supply Range
Positive Supply Current
−500
12
5
±15
+500
pF
pF
nA
V
INH
V
INL
V
HYST
I
IN
C
IN
V
OH
V
OL
V
LOGIC
= 1.8 V to 2.3 V
V
LOGIC
= 2.3 V to 5.5 V
0.8 × V
LOGIC
0.7 × V
LOGIC
0.2 × V
LOGIC
0.1 × V
LOGIC
±1
5
V
V
V
V
µA
pF
V
V
V
µA
pF
V
V
V
V
µA
nA
µA
mA
µA
nA
µW
dB
R
PULL-UP
= 2.2 kΩ to V
LOGIC
I
SINK
= 3 mA
I
SINK
= 6 mA, V
LOGIC
> 2.3 V
−1
V
LOGIC
0.4
0.6
+1
2
V
SS
= GND
Single supply, V
SS
= GND
Dual supply, V
SS
< GND
V
IH
= V
LOGIC
or V
IL
= GND
V
DD
= 5.5 V
V
DD
= 2.3 V
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
V
IH
= V
LOGIC
or V
IL
= GND
∆V
DD
/∆V
SS
= V
DD
± 10%,
code = full scale
2.3
±2.25
1.8
2.25
0.7
400
−0.7
2
320
1
3.5
−66
5.5
±2.75
V
DD
V
DD
5.5
I
DD
Negative Supply Current
EEPROM Store Current
3, 6
EEPROM Read Current
3, 7
Logic Supply Current
Power Dissipation
8
Power Supply Rejection Ratio
I
SS
I
DD_EEPROM_STORE
I
DD_EEPROM_READ
I
LOGIC
P
DISS
PSRR
−5.5
120
−60
Rev. A | Page 4 of 32
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS
9
Bandwidth
Symbol
BW
Test Conditions/Comments
−3 dB
R
AB
= 10 kΩ
R
AB
= 100 kΩ
V
DD
/V
SS
= ±2.5 V, V
A
= 1 V rms,
V
B
= 0 V, f = 1 kHz
R
AB
= 10 kΩ
R
AB
= 100 kΩ
Code = half scale, T
A
= 25°C,
f = 10 kHz
R
AB
= 10 kΩ
R
AB
= 100 kΩ
V
A
= 5 V, V
B
= 0 V, from
zero scale to full scale,
±0.5 LSB error band
R
AB
= 10 kΩ
R
AB
= 100 kΩ
T
A
= 25°C
100
Data Retention
1
2
AD5121/AD5141
Min
Typ
1
Max
Unit
3
0.43
MHz
MHz
Total Harmonic Distortion
THD
−80
−90
dB
dB
Resistor Noise Density
e
N_WB
7
20
nV/√Hz
nV/√Hz
V
W
Settling Time
t
S
Endurance
10
11
2
12
1
50
µs
µs
Mcycles
kcycles
Years
Typical values represent average readings at 25°C, V
DD
= 5 V, V
SS
= 0 V, and V
LOGIC
= 5 V.
Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × V
DD
)/R
AB
.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at V
WB
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6
Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7
Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8
P
DISS
is calculated from (I
DD
× V
DD
) + (I
LOGIC
× V
LOGIC
).
9
All dynamic characteristics use V
DD
/V
SS
= ±2.5 V, and V
LOGIC
= 2.5 V.
10
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11
Retention lifetime equivalent at junction temperature (T
J
) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
