DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
Resolution
N
DNL
Differential Nonlinearity
4
Integral Nonlinearity
4
INL
Code = 80
H
Voltage Divider Temperature Coefficient
∆V
W
/∆T
Code = FF
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
A, B
Capacitance
6
W
Shutdown Supply Current
Common-Mode Leakage
V
A, B, W
C
A, B
C
W
I
DD_SD
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
LOGIC
V
DD RANGE
V
DD/SS RANGE
I
DD
I
SS
P
DISS
PSS
6, 9
8
–1
–2
±
1/4
±
1/2
5
–1.5 –0.5
0
+0.5
V
SS
+1
+2
0
+1.5
V
DD
7
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
V
DD
= 5.5 V
V
A
= V
B
= V
DD
/2
H
H
45
60
0.01
1
2.4
5
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time (10 kΩ/50 kΩ)
Resistor Noise Voltage Density
0.8
V
DD
= 3 V, V
SS
= 0 V
V
DD
= 3 V, V
SS
= 0 V
V
IN
= 0 V or 5 V
2.1
0.6
±
1
5
2.7
–0.3
±
2.3
5.5
5.5
±
2.7
15
40
15
40
0.2
–0.01 0.001 +0.01
600
100
0.003
2/9
9
V
SS
= 0 V
V
IH
= +5 V or V
IL
= 0 V
V
SS
= –5 V
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V, V
SS
= 0 V
∆V
DD
= +5 V
±
10%, Code = Midscale
R
AB
= 10 kΩ, Code = 80
H
R
AB
= 50 kΩ, Code = 80
H
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz, R
AB
= 10 kΩ
V
A
= 5 V, V
B
= 0 V,
±
1 LSB Error Band
R
WB
= 5 kΩ, RS = 0
BW_10 kΩ
BW_50 kΩ
THD
W
t
S
e
N_WB
NOTES
1
Typicals represent average readings at 25°C and V
DD
= 5 V, V
SS
= 0 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +2.7 V,
V
SS
= –2.7 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V. DNL
specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. A terminal is open-circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V, V
SS
= 0 V.
Specifications subject to change without notice.
–2–
REV. D
AD5200/AD5201
AD5201 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
2
R-INL
Resistor Integral Nonlinearity
∆R
AB
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
R
AB
/∆T
Wiper Resistance
R
W
(V
DD
= 5 V 10%, or 3 V 10%, V
SS
= 0 V, V
A
= +V
DD
, V
B
= 0 V,
–40 C < T
A
< +85 C unless otherwise noted.)
Min Typ
1
–0.5
±
0.05
–1
±
0.1
–30
500
50
6
–0.5
±
0.01
–1
±
0.02
5
–1/2 –1/4
0
+1/4
V
SS
Max
+0.5
+1
+30
100
Unit
LSB
LSB
%
ppm/°C
Ω
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
nA
V
V
V
V
µA
pF
V
V
V
µA
µA
mW
%/%
kHz
kHz
%
µs
nV√Hz
Conditions
R
WB
, V
A
= No Connect
R
WB
, V
A
= No Connect
T
A
= 25°C
V
AB
= V
DD
, Wiper = No Connect
V
DD
= 5 V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
N
Resolution
4
DNL
Differential Nonlinearity
5
5
Integral Nonlinearity
INL
Code = 10
H
Voltage Divider Temperature Coefficient
∆V
W
/∆T
Code = 20
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
6
Capacitance
7
A, B
Capacitance
7
W
Shutdown Supply Current
Common-Mode Leakage
V
A, B, W
C
A, B
C
W
I
DD_SD
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
LOGIC
V
DD RANGE
V
DD/SS RANGE
I
DD
I
SS
P
DISS
PSS
7, 10
+0.5
+1
0
+1/2
V
DD
8
f = 1 MHz, Measured to GND, Code = 10
f = 1 MHz, Measured to GND, Code = 10
V
DD
= 5.5 V
V
A
= V
B
= V
DD
/2
H
H
45
60
0.01
1
2.4
5
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
7
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time (10 kΩ/50 kΩ)
Resistor Noise Voltage Density
0.8
V
DD
= 3 V, V
SS
= 0 V
V
DD
= 3 V, V
SS
= 0 V
V
IN
= 0 V or 5 V
2.1
0.6
±
1
5
2.7
–0.3
±
2.3
5.5
5.5
±
2.7
15
40
15
40
0.2
–0.01 0.001 +0.01
600
100
0.003
2/9
9
V
SS
= 0 V
V
IH
= +5 V or V
IL
= 0 V
V
SS
= –5 V
V
IH
= +5 V or V
IL
= 0 V, V
DD
= +5 V, V
SS
= –5 V
∆V
DD
= +5 V
±
10%
R
AB
= 10 kΩ, Code = 10
H
R
AB
= 50 kΩ, Code = 10
H
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz, R
AB
= 10 kΩ
V
A
= 5 V, V
B
= 0 V,
±
1 LSB Error Band
R
WB
= 5 kΩ, RS = 0
BW_10 kΩ
BW_50 kΩ
THD
W
t
S
e
N_WB
NOTES
1
Typicals represent average readings at 25°C and V
DD
= 5 V, V
SS
= 0 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
= +2.7 V,
V
SS
= –2.7 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
Six bits are needed for 33 positions even though it is not a 64-position device.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V. DNL
specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions.
6
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
7
Guaranteed by design and not subject to production test.
8
Measured at the A terminal. A terminal is open-circuited in shutdown mode.
9
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= 5 V, V
SS
= 0 V.
Specifications subject to change without notice.
REV. D
–3–
AD5200/AD5201–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(V
DD
= 5 V 10%, or 3 V
unless otherwise noted.)
Conditions
10%, V
SS
= 0 V, V
A
= +V
DD
, V
B
= 0 V, –40 C < T
A
< +85 C
Min
20
5
5
15
40
0
0
10
Typ
1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])
Input Clock Pulsewidth
t
CH
, t
CL
Clock Level High or Low
Data Setup Time
t
DS
Data Hold Time
t
DH
CS
Setup Time
t
CSS
CS
High Pulsewidth
t
CSW
CLK Fall to
CS
Fall Hold Time
t
CSH0
CLK Fall to
CS
Rise Hold Time
t
CSH1
CS
Rise to Clock Rise Setup
t
CS1
NOTES
1
Typicals represent average readings at 25°C and V
DD
= 5 V, V
SS
= 0 V.
2
Guaranteed by design and not subject to production test.
3
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using V
