2.5 V to 5.5 V, 500 μA, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305/AD5315/AD5325
FEATURES
AD5305: 4 buffered 8-bit DACs in 10-lead MSOP
A version: ±1 LSB INL, B version: ±0.625 LSB INL
AD5315: 4 buffered 10-bit DACs in 10-lead MSOP
A version: ±4 LSB INL, B version: ±2.5 LSB INL
AD5325: 4 buffered 12-bit DACs in 10-lead MSOP
A version: ±16 LSB INL, B version: ±10 LSB INL
Low power operation: 500 μA @ 3 V, 600 μA @ 5 V
2-wire (I
2
C®-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
Three power-down modes
Double-buffered input logic
Output range: 0 V to V
REF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325
1
are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface that
operates at clock rates up to 400 kHz is used. This interface is
SMBus compatible at V
DD
< 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one
reference pin. The outputs of all DACs can be updated
simultaneously using the software LDAC function.
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power up to 0 V and remain there until a
valid write takes place to the device. There is also a software
clear function to reset all input and DAC registers to 0 V. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated equip-
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 μW in power-down mode.
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
V
DD
LDAC
DAC
REGISTER
1
Protected by U.S. Patent No. 5,969,657 and 5,684,481.
FUNCTIONAL BLOCK DIAGRAM
REF IN
INPUT
REGISTER
STRING
DAC A
BUFFER
V
OUT
A
SCL
SDA
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
V
OUT
D
POWER-ON
RESET
AD5305/AD5315/AD5325
GND
POWER-DOWN
LOGIC
00930-001
Figure 1.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD5305/AD5315/AD5325
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Functional Description .................................................................. 15
Digital-to-Analog Section ......................................................... 15
Resistor String ............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-On Reset .......................................................................... 15
Serial Interface ............................................................................ 16
Read/Write Sequence................................................................. 16
Pointer Byte Bits ......................................................................... 16
Input Shift Register .................................................................... 16
Default Readback Condition .................................................... 17
Multiple-DAC Write Sequence................................................. 17
Multiple-DAC Readback Sequence ......................................... 17
Write Operation.......................................................................... 17
Read Operation........................................................................... 17
Double-Buffered Interface ........................................................ 18
Power-Down Modes .................................................................. 18
Applications..................................................................................... 20
Typical Application Circuit....................................................... 20
Bipolar Operation....................................................................... 20
Multiple Devices on One Bus ................................................... 20
AD5305/AD5315/AD5325 as a Digitally Programmable
Window Detector ....................................................................... 21
Coarse and Fine Adjustment Using the
AD5305/AD5315/AD5325 ....................................................... 21
Power Supply Decoupling ......................................................... 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
5/06—Rev. F to Rev. G
Updated Format..................................................................Universal
Changes to Ordering Guide .......................................................... 24
10/04—Rev. E to Rev. F
Changes to Figure 6........................................................................ 11
Changes to Pointer Byte Bits Section ........................................... 12
Changes to Figure 7........................................................................ 12
8/03—Rev. D to Rev. E
Added A Version.................................................................Universal
Changes to Features.......................................................................... 1
Changes to Specifications ................................................................ 2
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Ordering Guide ............................................................ 5
Changes to TPC 21......................................................................... 10
Added Octals Section to Table II.................................................. 18
Updated Outline Dimensions....................................................... 19
4/01—Rev. C to Rev. D
Edit to Features Section ....................................................................1
Edit to Figure 6 ..................................................................................1
Edits to Right/Left and Double Sections
of Pointer Byte Bits Section........................................................... 11
Edit to Input Shift Register Section.............................................. 12
Edit to Multiple-DAC Readback Sequence Section................... 12
Edits to Figure 7.............................................................................. 12
Edits to Write Operation section.................................................. 13
Edits to Figure 8.............................................................................. 13
Edits to Read Operation section................................................... 14
Edits to Figure 9.............................................................................. 14
Edits to Power-Down Modes section .......................................... 15
Edits to Figure 12............................................................................ 16
Rev. G | Page 2 of 24
AD5305/AD5315/AD5325
SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V, V
REF
= 2 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
2
DC PERFORMANCE
3, 4
AD5305
Resolution
Relative Accuracy
Differential Nonlinearity
AD5315
Resolution
Relative Accuracy
Differential Nonlinearity
AD5325
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Offset Error Drift
5
Gain Error Drift
5
Power Supply Rejection Ratio
5
DC Crosstalk
5
DAC REFERENCE INPUTS
5
V
REF
Input Range
V
REF
Input Impedance
Reference Feedthrough
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
6
Min
A Version
1
Typ
Max
Min
B Version
1
Typ
Max
Unit
Conditions/Comments
8
±0.15
±0.02
±1
±0.25
8
±0.15
±0.02
±0.625
±0.25
Bits
LSB
LSB
Guaranteed monotonic by design
over all codes
10
±0.5
±0.05
±4
±0.5
10
±0.5
±0.05
±2.5
±0.5
Bits
LSB
LSB
Guaranteed monotonic by design
over all codes
12
±2
±0.2
±0.4
±0.15
20
−12
−5
–60
200
0.25
37
±16
±1
±3
±1
60
12
±2
±0.2
±0.4
±0.15
20
−12
−5
–60
200
±10
±1
±3
±1
60
Bits
LSB
LSB
% of FSR
% of FSR
mV
ppm of
FSR/°C
ppm of
FSR/°C
dB
μV
Guaranteed monotonic by design
over all codes
Lower deadband exists only if offset
error is negative
∆V
DD
= ±10%
R
L
= 2 kΩ to GND or V
DD
V
DD
45
>10
−90
0.001
0.25
37
V
DD
45
>10
−90
0.001
V
kΩ
MΩ
dB
V
Normal operation
Power-down mode
Frequency = 10 kHz
A measure of the minimum and
maximum drive capability of the
output amplifier
Maximum Output Voltage
6
DC Output Impedance
Short-Circuit Current
Power-Up Time
V
DD
−
0.001
0.5
25
16
2.5
5
V
DD
−
0.001
0.5
25
16
2.5
5
V
Ω
mA
mA
μs
μs
V
DD
= 5 V
V
DD
= 3 V
Coming out of power-down mode
V
DD
= 5 V
Coming out of power-down mode
V
DD
= 3 V
Rev. G | Page 3 of 24
AD5305/AD5315/AD5325
Parameter
2
LOGIC INPUTS (A0)
5
Input Current
Input Low Voltage, V
IL
Min
A Version
1
Typ
Max
±1
0.8
0.6
0.5
2.4
2.1
2.0
3
0.7
V
DD
−0.3
0.05
V
DD
8
50
V
DD
+
0.3
0.3 V
DD
±1
0.7
V
DD
−0.3
0.05
V
DD
8
50
2.4
2.1
2.0
3
V
DD
+
0.3
0.3 V
DD
±1
Min
B Version
1
Typ
Max
±1
0.8
0.6
0.5
Unit
μA
V
V
V
V
V
V
pF
V
V
μA
V
pF
ns
Conditions/Comments
Input High Voltage, V
IH
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2.5 V
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2.5 V
Pin Capacitance
LOGIC INPUTS (SCL, SDA)
5
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Leakage Current, I
IN
Input Hysteresis, V
HYST
Input Capacitance, C
IN
Glitch Rejection
LOGIC OUTPUT (SDA)
5
Output Low Voltage, V
OL
Three-State Leakage Current
Three-State Output
Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
7
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
1
2
SMBus compatible at V
DD
< 3.6 V
SMBus compatible at V
DD
< 3.6 V
Input filtering suppresses noise spikes
of less than 50 ns
I
SINK
= 3 mA
I
SINK
= 6 mA
0.4
0.6
±1
8
8
0.4
0.6
±1
V
V
μA
pF
2.5
600
500
0.2
0.08
5.5
900
700
1
1
2.5
600
500
0.2
0.08
5.5
900
700
1
1
V
V
IH
= V
DD
and V
IL
= GND
μA
μA
μA
μA
V
IH
= V
DD
and V
IL
= GND
I
DD
= 4 μA (maximum) during
0 readback on SDA
I
DD
= 1.5 μA (maximum) during
0 readback on SDA
Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
See the Terminology section.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error must be
positive.
7
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. G | Page 4 of 24
AD5305/AD5315/AD5325
AC CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
2, 3
Output Voltage Settling Time
AD5305
AD5315
AD5325
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
A, B Version
1
Min
Typ
Max
6
7
8
0.7
12
1
1
3
200
−70
8
9
10
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
Conditions/Comments
V
REF
= V
DD
= 5 V
¼ scale to ¾ scale change (0×40 to 0×C0)
¼ scale to ¾ scale change (0×100 to 0×300)
¼ scale to ¾ scale change (0×400 to 0×C00)
1 LSB change around major carry
V
REF
= 2 V ± 0.1 V p-p
V
REF
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization, not production tested.
3
See the Terminology section.
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6 3
t
7
t
8
t
9
t
10
t
11
Limit at T
MIN
, T
MAX
(A, B Version)
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 C
B 4
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD,STA
, start/repeated start condition hold time
t
SU,DAT
, data setup time
t
HD,DAT
, data hold time
t
HD,DAT
, data hold time
t
SU,STA
, setup time for repeated start
t
SU,STO
, stop condition setup time
t
BUF
, bus-free time between a stop and a start condition
t
R
, rise time of SCL and SDA when receiving
t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
F
, fall time of SDA when transmitting
t
F
, fall time of SDA when receiving (CMOS compatible)
t
F
, fall time of SCL and SDA when receiving
t
F
, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
C
B4
1
2
See Figure 2.
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
4
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Rev. G | Page 5 of 24
