, unless otherwise noted. DC performance measured with OP177, AC
performance with AD8038, unless otherwise noted.)
Parameter
STATIC PERFORMANCE
AD5426
Resolution
Relative Accuracy
Differential Nonlinearity
AD5432
Resolution
Relative Accuracy
Differential Nonlinearity
AD5443
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
2
Output Leakage Current
REFERENCE INPUT
2
Reference Input Range
V
REF
Input Resistance
R
FB
Resistance
Input Capacitance
Code All 0s
Code All 1s
DIGITAL INPUTS/OUTPUT
2
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Leakage Current, I
IL
Input Capacitance
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
Output High Voltage, V
OH
V
DD
= 3 V to 3.6 V
Output Low Voltage, V
OL
Output High Voltage, V
OH
DYNAMIC PERFORMANCE
2
Reference Multiplying Bandwidth
Output Voltage Settling Time
AD5426
AD5432
AD5443
Digital Delay
10% to 90% Rise/Fall Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Min
Typ
Max
Unit
Conditions
8
±
0.25
±
0.5
10
±
0.5
±
1
12
±
1
–1/+2
±
10
±
5
±
25
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
kΩ
kΩ
pF
pF
V
V
A
pF
V
V
V
V
MHz
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
±
5
Data = 0x0000, T
A
= 25°C, I
OUT
Data = 0x0000, I
OUT
8
8
±
10
10
10
3
5
12
12
6
8
Input resistance TC = –50 ppm/°C
Input resistance TC = –50 ppm/°C
1.7
0.6
2
10
0.4
V
DD
– 1
0.4
V
DD
– 0.5
10
50
55
90
40
15
2
70
48
100
110
160
75
30
4
I
SINK
= 200 A
I
SOURCE
= 200 A
I
SINK
= 200 A
I
SOURCE
= 200 A
V
REF
=
±
3.5 V; DAC loaded all 1s
V
REF
= 10 V; R
LOAD
= 100
Ω,
C
LOAD
= 15 pF
Measured to
±16
mV of full scale
Measured to
±
4 mV of full scale
Measured to
±
1 mV of full scale
Interface Delay Time
Rise and fall time, V
REF
= 10 V, R
LOAD
= 100
Ω
1 LSB change around major carry, V
REF
= 0 V
DAC latch loaded with all 0s. V
REF
=
±3.5
V
1 MHz
10 MHz
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with
SYNC
high and
alternate loading of all 0s and all 1s
V
REF
= 3.5 V pk-pk; all 1s loaded, f = 1 kHz
ns
ns
ns
ns
ns
nV-s
dB
dB
Output Capacitance
I
OUT
2
I
OUT
1
Digital Feedthrough
Total Harmonic Distortion
Digital THD Clock = 1 MHz
50 kHz f
OUT
Output Noise Spectral Density
22
10
12
25
0.1
–81
73
25
25
12
17
30
pF
pF
pF
pF
nV-s
dB
dB
nV/√Hz
@ 1 kHz
–2–
REV. 0
AD5426/AD5432/AD5443
Parameter
SFDR Performance (Wide Band)
Clock = 10 MHz
50 kHz f
OUT
20 kHz f
OUT
SFDR Performance (Narrow Band)
Clock = 1 MHz
50 kHz f
OUT
20 kHz f
OUT
Intermodulation Distortion
Clock = 1 MHz
f
1
= 20 kHz, f
2
= 25 kHz
POWER REQUIREMENTS
Power Supply Range
I
DD
3.0
0.4
Min
Typ
Max
Unit
Conditions
AD5443, 4096 codes V
REF
= 3.5 V
75
76
dB
dB
87
87
dB
dB
78
5.5
5
0.6
dB
V
A
A
Logic inputs = 0 V or V
DD
T
A
= 25°C, logic inputs = 0 V or V
DD
NOTES
1
Temperature range is as follows: Y version: –40°C to +125°C.
2
Guaranteed by design and characterization, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
AD5426/AD5432/AD5443
TIMING CHARACTERISTICS
1
(V
Parameter
f
SCLK
t
1
t
2
t
3
t
4 2
t
5
t
6
t
7
t
8
t
9 3
3.0 V to 5.5 V
50
20
8
8
13
5
3
5
30
80
120
50
20
8
8
13
5
3
5
30
45
65
DD
= 3 V to 5.5 V, V
REF
= 10 V, I
OUT
2 = O V. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
Conditions/Comments
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC
falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC
rising edge to SCLK active edge
Minimum
SYNC
high time
SCLK active edge to SDO valid
4.5 V to 5.5 V
NOTES
1
See Figures 1 and 2. Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Falling or rising edge as determined by control bits of serial word.
3
Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
t
1
SCLK
t
2
t
8
t
4
SYNC
t
3
t
7
t
6
t
5
DIN
DB15
DB0
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Standalone Mode Timing Diagram
t
1
SCLK
t
2
t
4
SYNC
t
3
t
7
t
8
t
6
t
5
SDIN
DB15 (N)
DB0 (N)
DB15
(N+1)
DB0 (N+1)
t
9
SDO
DB15(N)
DB0(N)
ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 2. Daisy-chain and Readback Modes Timing Diagram
–4–
REV. 0
AD5426/AD5432/AD5443
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
200 A
TO
OUTPUT
PIN
I
OL
V
OH (MIN)
+ V
OL (MAX)
C
L
20pF
200 A
I
OH
2
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
REF
, R
FB
to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V
I
OUT
1, I
OUT
2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
嵌入式系统
