Data Sheet
FEATURES
10 MHz multiplying bandwidth
INL of ±0.25 LSB @ 8 bits
20-lead and 24-lead TSSOP packages
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Readback function
AD7528 upgrade (AD5428)
AD7547 upgrade (AD5447)
Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Parallel Interface
AD5428/AD5440/AD5447
GENERAL DESCRIPTION
The AD5428/AD5440/AD5447
1
are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DACs),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
As a result of being manufactured on a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The DACs use data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The applied external reference input voltage (V
REF
) determines
the full-scale output current. An integrated feedback resistor (R
FB
)
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier.
The AD5428 is available in a small 20-lead TSSOP package, and
the AD5440/AD5447 DACs are available in small 24-lead TSSOP
packages.
1
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
V
REF
A
AD5428/AD5440/AD5447
V
DD
DATA
INPUTS
DB0
DB7
DB9
DB11
R
R
FB
A
I
OUT
A
INPUT
BUFFER
LATCH
8-/10-/12-BIT
R-2R DAC A
AGND
DAC A/B
R
CS
R/W
LATCH
DGND
CONTROL
LOGIC
8-/10-/12-BIT
R-2R DAC B
R
FB
B
I
OUT
B
POWER-ON
RESET
04462-001
V
REF
B
Figure 1. AD5428/AD5440/AD5447
Rev. C
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AD5428_5440_5447*
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DOCUMENTATION
AN-912:
Driving a Center-Tapped Transformer with a Balanced
Current-Output D
AN-320A:
CMOS Multiplying DACs and Op Amps Combine to Build
Programmable Gain Amplifier, Part 1
AN-137:
A Digitally Programmable Gain and Attenuation Amplifier
Design
UG-275:
Evaluation Board for the AD5428/AD5440/AD5447EB
8-Bit/10-Bit/12-Bit, Parallel Input, Dual-Channel, Current Output DAC
4-Quadrant Multiplying D/A Converters
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AD5428/AD5440/AD5447
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 15
General Description ....................................................................... 16
DAC Section................................................................................ 16
Circuit Operation ....................................................................... 16
Single-Supply Applications ....................................................... 19
Adding Gain................................................................................ 19
Data Sheet
Divider or Programmable Gain Element................................ 20
Reference Selection .................................................................... 20
Amplifier Selection .................................................................... 20
Parallel Interface......................................................................... 22
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 23
Evaluation Board for the AD5447............................................ 23
Power Supplies for the Evaluation Board................................ 23
Bill of Materials............................................................................... 27
Overview of AD54xx Devices....................................................... 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
8/11—Rev. B to Rev. C
Changes to CS Pin Description, Table 6 ........................................ 9
3/11—Rev. A to Rev. B
Changes to Evaluation Board For the AD5447 Section ............ 23
Changes to Figure 47 Caption....................................................... 24
Changes to Figure 49...................................................................... 25
Change to U1 Description in Table 12......................................... 27
Change to Ordering Guide............................................................ 29
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC A/B................................Universal
Changes to Features List .................................................................. 1
Changes to Specifications ................................................................ 3
Changes to Timing Characteristics ................................................ 5
Change to Figure 2 ........................................................................... 5
Change to Absolute Maximum Ratings Section........................... 6
Change to Figure 13, Figure 14, and Figure 18........................... 11
Change to Figure 32 Through Figure 34 ..................................... 14
Changes to General Description Section .................................... 16
Changes to Figure 37...................................................................... 16
Changes to Single-Supply Applications Section......................... 19
Changes to Figure 40 Through Figure 42.................................... 19
Changes to Divider or Programmable Gain Element Section .... 20
Changes to Figure 43...................................................................... 20
Changes to Table 9 Through Table 11 ......................................... 21
Changes to Microprocessor Interfacing Section ........................ 22
Added Figure 44 Through Figure 46 ........................................... 22
Added 8xC51-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Added ADSP-BF5xx-to-AD5428/AD5440/AD5447
Interface Section ........................................................................ 22
Changes to Power Supplies for the Evaluation Board Section.... 23
Changes to Table 13 ....................................................................... 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide .......................................................... 29
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet
SPECIFICATIONS
1
AD5428/AD5440/AD5447
V
DD
= 2.5 V to 5.5 V, V
REF
= 10 V, I
OUT
2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
AD5428
Resolution
Relative Accuracy
Differential Nonlinearity
AD5440
Resolution
Relative Accuracy
Differential Nonlinearity
AD5447
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Output Leakage Current
REFERENCE INPUT
Reference Input Range
V
REF
A, V
REF
B Input Resistance
V
REF
A-to-V
REF
B Input
Resistance Mismatch
Input Capacitance
Code 0
Code 4095
DIGITAL INPUTS/OUTPUT
Input High Voltage, V
IH
Input Low Voltage, V
IL
Output High Voltage, V
OH
Output Low Voltage, V
OL
Input Leakage Current, I
IL
Input Capacitance
DYNAMIC PERFORMANCE
Reference-Multiplying BW
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
V
DD
− 1
V
DD
− 0.5
0.4
0.4
1
10
Min
Typ
Max
Unit
Conditions
8
±0.25
±1
10
±0.5
±1
12
±1
–1/+2
±25
±5
±5
±15
±10
10
1.6
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
kΩ
%
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0x0000, T
A
= 25°C
Data = 0x0000
8
13
2.5
Input resistance TC = –50 ppm/°C
Typ = 25°C, max = 125°C
3.5
3.5
1.7
1.7
0.8
0.7
pF
pF
V
V
V
V
V
V
V
V
μA
pF
MHz
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.5 V to 2.7 V
V
DD
= 4.5 V to 5.5 V, I
SOURCE
= 200 μA
V
DD
= 2.5 V to 3.6 V, I
SOURCE
= 200 μA
V
DD
= 4.5 V to 5.5 V, I
SINK
= 200 μA
V
DD
= 2.5 V to 3.6 V, I
SINK
= 200 μA
4
10
V
REF
= ±3.5 V p-p, DAC loaded all 1s
R
LOAD
= 100 Ω, C
LOAD
= 15 pF, V
REF
= 10 V
DAC latch alternately loaded with 0s and 1s
80
35
30
20
15
3
120
70
60
40
30
ns
ns
ns
ns
ns
nV-sec
Interface delay time
Rise and fall times, V
REF
= 10 V, R
LOAD
= 100 Ω
1 LSB change around major carry, V
REF
= 0 V
Rev. C | Page 3 of 32
AD5428/AD5440/AD5447
Parameter
Multiplying Feedthrough Error
Min
Typ
Max
70
48
17
30
Unit
dB
dB
pF
pF
nV-sec
nV/√Hz
dB
dB
dB
AD5447, 65k codes, V
REF
= 3.5 V
55
63
65
50
60
62
dB
dB
dB
dB
dB
dB
AD5447, 65k codes, V
REF
= 3.5 V
73
80
87
70
75
80
72
65
2.5
0.5
Power Supply Sensitivity
1
Data Sheet
Conditions
DAC latches loaded with all 0s, V
REF
= ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
V
REF
= 3.5 V p-p, all 1s loaded, f = 100 kHz
Clock = 10 MHz, V
REF
= 3.5 V
Output Capacitance
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz f
OUT
50 kHz f
OUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
Clock = 25 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz f
OUT
100 kHz f
OUT
50k Hz f
OUT
Clock = 25 MHz
500 kHz f
OUT
100 kHz f
OUT
50 kHz f
OUT
Intermodulation Distortion
f
1
= 40 kHz, f
2
= 50 kHz
f
1
= 40 kHz, f
2
= 50 kHz
POWER REQUIREMENTS
Power Supply Range
I
DD
12
25
1
25
81
61
66
dB
dB
dB
dB
dB
dB
dB
dB
5.5
0.7
10
0.001
V
μA
μA
%/%
AD5447, 65k codes, V
REF
= 3.5 V
Clock = 10 MHz
Clock = 25 MHz
T
A
= 25°C, logic inputs = 0 V or V
DD
T
A
= −40°C to +125°C, logic inputs = 0 V or V
DD
∆V
DD
= ±5%
Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 32
