True Accuracy, 16-Bit ±12 V/±15 V,
Serial Input Voltage Output DAC
AD5570
FEATURES
Full 16-bit performance
1 LSB maximum INL and DNL
Output voltage range up to ±14 V
On-board reference buffers, eliminating the need for a
negative reference
Controlled output during power-on
Temperature ranges of −40°C to +85°C for A/B version/−40°C
to +125°C for W/Y version
Settling time of 10 μs to 0.003%
Clear function to 0 V
Asynchronous update of outputs (LDAC pin)
Power-on reset
Serial data output for daisy chaining
Data readback facility
5 kV HBM ESD classification
FUNCTIONAL BLOCK DIAGRAM
V
SS
V
DD
DGND
AD5570
REFGND
POWER-ON
RESET
2R
16-BIT
DAC
V
OUT
AGND
AGNDS
R
R
REFIN
DAC REGISTER
POWER-DOWN
CONTROL LOGIC
LDAC
SHIFT REGISTER
PD
SDIN
SCLK
SYNC
SDO
CLR
Figure 1.
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
Data acquisition systems
General-purpose instrumentation
GENERAL DESCRIPTION
The AD5570 is a single 16-bit serial input, voltage output DAC
that operates from supply voltages of ±11.4 V up to ±16.5 V.
Integral linearity (INL) and differential nonlinearity (DNL) are
accurate to 1 LSB. During power-up, when the supply voltages
are changing, V
OUT
is clamped to 0 V via a low impedance path.
The AD5570 DAC comes complete with a set of reference
buffers. The reference buffers allow a single, positive reference
to be used. The voltage on REFIN is gained up and inverted
internally to give the positive and negative reference for the
DAC core. Having the reference buffers on-chip eliminates the
need for external components such as inverters, precision
amplifiers, and resistors, thereby reducing the overall solution
size and cost.
The AD5570 uses a versatile 3-wire interface that is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards.
Data is presented to the part as a 16-bit serial word. Serial data
is available on the SDO pin for daisy-chaining purposes. Data
readback allows the user to read the contents of the DAC
register via the SDO pin.
Features on the AD5570 include LDAC which is used to update
the output of the DAC. The device also has a power-down pin
(PD), allowing the DAC to be put into a low power state, and a
CLR pin that allows the output to be cleared to 0 V.
The AD5570 is available in a 16-lead SSOP.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
1 LSB maximum INL and DNL.
Buffered voltage output up to ±14 V.
Output controlled during power-up.
On-board reference buffers.
Wide temperature range of
−40°C
to +125°C.
5 kV HBM ESD classification.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
03760-001
AD5570
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Standalone ..................................................................................... 5
Timing Characteristics..................................................................... 6
Daisy-Chaining and Readback ................................................... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 11
General Description ....................................................................... 16
DAC Architecture....................................................................... 16
Reference Buffers........................................................................ 16
Serial Interface ............................................................................ 16
Transfer Function....................................................................... 17
Clear (CLR) ................................................................................. 17
Power-Down (PD) ..................................................................... 17
Power-On Reset.......................................................................... 17
Serial Data Output (SDO)......................................................... 17
Applications Information .............................................................. 19
Typical Operating Circuit ......................................................... 19
Layout Guidelines....................................................................... 20
Opto-Isolators............................................................................. 20
Microprocessor Interfacing....................................................... 21
Evaluation Board ........................................................................ 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
11/10—Rev. B to Rev. C
Added HBM ESD Classification to Features and Product
Highlights Section ............................................................................ 1
Added ESD Parameter to Table 4 ................................................... 8
Changes to Ordering Guide .......................................................... 24
9/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 3............................................................................ 6
Changes to Figure 43...................................................................... 21
Changes to AD5570 to 8xC51 Interface Section ........................ 21
Changes to Ordering Guide .......................................................... 24
4/05—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Table 4............................................................................ 8
Added Figure 16.............................................................................. 12
Revision 0: Initial Version
Rev. C | Page 2 of 24
AD5570
SPECIFICATIONS
V
DD
= +11.4 V to +16.5 V, V
SS
= −11.4 V to −16.5 V, V
REF
= 5 V, REFGND = AGND = DGND = 0 V, R
L
= 5 kΩ, C
L
= 200 pF to AGND;
all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
1
ACCURACY
Resolution
Monotonicity
Differential Nonlinearity (DNL)
Relative Accuracy (INL)
B/Y Grade
A/W Grade
Positive INL Drift Over Time
3
A/B Grades
W/Y Grades
Negative Full-Scale Error
Full-Scale Error
Bipolar Zero Error
Gain Error
Gain Temperature Coefficient
4
REFERENCE INPUT
Reference Input Range
4
Input Current
OUTPUT CHARACTERISTICS
4
Output Voltage Range
Output Voltage Settling Time
Min
Typ
2
Max
Unit
Bits
Bits
LSB
LSB
LSB
Test Conditions/Comments
16
16
−1
−1
−2
±0.3
±0.4
±0.6
2.5
6.5
±0.9
±1.8
±0.9
±1.8
+0.25
+1
+1
+2
See Figure 16
ppm
ppm
mV
mV
mV
mV
ppm FSR/°C
V
V
μA
V
V
μs
μs
μs
V/μs
nV-s
kHz
mA
nV/Hz
Ω
nV-s
sec
μA
V
V
pF
V
pF
I
SINK
= 1 mA
With ±11.4 V supplies
With ±16.5 V supplies
±7.5
±6
±7.5
±7.5
±1.5
5
7
±0.1
V
DD
− 1.4
V
DD
− 2.5
16
13
7
4
4
5
5
V
SS
+ 1.4
V
SS
+ 2.5
12
10
6
6.5
15
20
25
85
0.35
0.5
12
Slew Rate
Digital-to-Analog Glitch Impulse
Bandwidth
Short Circuit Current
Output Noise Voltage Density
DAC Output Impedance
Digital Feedthrough
WARMUP TIME
5
LOGIC INPUTS
Input Currents
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OL
, Output Low Voltage
Floating-State Output
With ±11.4 V supplies
With ±16.5 V supplies
At 16 bits to ±0.5 LSB
To 0.0003%
512 LSB code change
Measured from 10% to 90%
±12 V supplies; 1 LSB change around
the major carry
f = 1 kHz; midscale loaded
0.5
±0.1
2
0.8
3
0.4
8
Rev. C | Page 3 of 24
AD5570
Parameter
1
POWER REQUIREMENTS
V
DD
/V
SS
I
DD
I
SS
Power-Down Current
Power-Supply Sensitivity
6
Power Dissipation
1
2
Min
Typ
2
Max
Unit
V
mA
mA
μA
LSB/V
mW
Test Conditions/Comments
±11.4
4
3.5
16
0.1
100
±16.5
5
5
V
OUT
unloaded
V
OUT
unloaded
V
OUT
unloaded
±15 supplies ±10%; full-scale loaded
V
OUT
unloaded
Temperature ranges: A and B versions = − 40°C to +85°C; W and Y versions = −40°C to +125°C.
Typical specifications at ±12 V/±15 V, +25°C.
3
These numbers are generated from the life test of the part.
4
Guaranteed by design.
5
Warmup time is required for the device to reach thermal equilibrium, thus achieving rated performance.
6
Sensitivity of negative full-scale error and positive full-scale error to V
DD
, V
SS
variations.
Rev. C | Page 4 of 24
AD5570
TIMING CHARACTERISTICS
STANDALONE
V
DD
= +12 V ± 5%, V
SS
= −12 V ± 5% or V
DD
= +15 V ± 10%, V
SS
= −15 V ± 10%, V
REF
= 5 V, REFGND = AGND = DGND = 0 V, R
L
= 5 kΩ,
C
L
= 200 pF to AGND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
1
2
1, 2
Limit at T
MIN
, T
MAX
10
100
35
35
10
35
0
45
45
0
50
0
0
20
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
LDAC falling edge to SYNC falling edge (no update)
LDAC rising edge to SYNC rising edge (no update)
CLR pulse width
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+V
IH
)/2.
t
1
SCLK
t
2
t
8
SYNC
t
3
t
7
t
4
t
6
t
5
SDIN
DB15
DB0
t
9
LDAC
1
t
10
t
11
LDAC
2
t
12
CLR
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2
SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
t
13
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 5 of 24
03760-002
