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Data Sheet

FEATURES

Octal, 16-Bit

nanoDAC+

with SPI Interface

AD5676

GENERAL DESCRIPTION

The AD5676 is a low power, octal, 16-bit buffered voltage

output digital-to-analog converter (DAC). The device includes

a gain select pin, giving a full-scale output of V

REF

(gain = 1) or

2 × V

REF

(gain = 2). The AD5676 DAC operates from a single

2.7 V to 5.5 V supply and is guaranteed monotonic by design.

The AD5676 is available in 20-lead TSSOP and LFCSP packages.

The internal power-on reset circuit and the RSTSEL pin of the

AD5676 ensure that the output DACs power up to zero scale or

midscale and then remain there until a valid write takes place. The

AD5676 contains a per channel power-down mode that typically

reduces the current consumption of the device to 1 µA.

The AD5676 employs a versatile serial peripheral interface (SPI)

that operates at clock rates up to 50 MHz, and contains a V

LOGIC

intended for 1.62 V to 5.5 V logic.

Table 1. Octal

nanoDAC+®

Devices

Interface

SPI

Reference

Internal

External

Internal

External

16-Bit

AD5676R

AD5676

AD5675R

AD5675

12-Bit

AD5672R

Not applicable

AD5671R

Not applicable

High performance

High relative accuracy (INL): ±3 LSB maximum at 16 bits

Total unadjusted error (TUE): ±0.14% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.06% of FSR maximum

Wide operating ranges

−40°C to +125°C temperature range

2.7 V to 5.5 V power supply

Easy implementation

User selectable gain of 1 or 2 (GAIN pin/gain bit)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

50 MHz SPI with readback or daisy chain

20-lead, TSSOP and LFCSP RoHS-compliant packages

APPLICATIONS

Optical transceivers

Base station power amplifiers

Process control (PLC input/output cards)

Industrial automation

Data acquisition systems

PRODUCT HIGHLIGHTS

High relative accuracy (INL) 16-bit: ±3 LSB maximum.

−40°C to +125°C temperature range.

20-lead, TSSOP and LFCSP RoHS-compliant packages.

REF

FUNCTIONAL BLOCK DIAGRAM

LOGIC

AD5676

INPUT

INTERFACE

LOGIC

SDI

INPUT

DAC

STRING

DAC 0

STRING

DAC 1

STRING

DAC 2

STRING

DAC 3

STRING

DAC 4

STRING

DAC 5

STRING

DAC 6

STRING

DAC 7

GAIN x1/x2

BUFFER

OUT

BUFFER

OUT

SCLK

BUFFER

OUT

SYNC

BUFFER

OUT

BUFFER

OUT

SDO

BUFFER

OUT

LDAC

BUFFER

OUT

RESET

BUFFER

OUT

POWER-ON RESET

POWER-DOWN

LOGIC

12549-001

RSTSEL

GAIN

GND

Figure 1.

Rev. D

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

AD5676

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 4

AC Characteristics ........................................................................ 6

Timing Characteristics ................................................................ 7

Daisy-Chain and Readback Timing Characteristics................ 8

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

Digital-to-Analog Converter .................................................... 21

Transfer Function ....................................................................... 21

DAC Architecture ....................................................................... 21

Serial Interface ............................................................................ 22

Data Sheet

Standalone Operation ................................................................ 23

Write and Update Commands .................................................. 23

Daisy-Chain Operation ............................................................. 23

Readback Operation .................................................................. 24

Power-Down Operation ............................................................ 24

Load DAC (Hardware LDAC Pin) ........................................... 25

LDAC Mask Register ................................................................. 25

Hardware Reset (RESET) .......................................................... 26

Reset Select Pin (RSTSEL) ........................................................ 26

Software Reset ............................................................................. 26

Amplifier Gain Selection on LFCSP Package ......................... 26

Applications Information .............................................................. 27

Power Supply Recommendations............................................. 27

Microprocessor Interfacing ....................................................... 27

AD5676 to ADSP-BF531 Interface .......................................... 27

AD5676 to SPORT Interface ..................................................... 27

Layout Guidelines....................................................................... 27

Galvanically Isolated Interface ................................................. 28

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

REVISION HISTORY

5/2018—Rev. C to Rev. D

Change to SYNC to SCLK Falling Edge Parameter, Table 5 ....... 8

4/2018—Rev. B to Rev. C

Changes to Features Section and General Description Section....... 1

Changes to Specifications Section .................................................. 4

Changes to V

LOGIC

Parameter, Table 2 ............................................ 5

Deleted Endnote 3, Table 2; Renumbered Sequentially .............. 5

Changes to AC Characteristics Section and Output Noise

Spectral Density (NSD) Parameter, Table 3 .................................. 6

Changes to Timing Characteristics Section, Table 4, and

Figure 2 .............................................................................................. 7

Changes to Daisy-Chain and Readback Timing Characteristics

Section, Table 5, Figure 3, and Figure 4 ......................................... 8

Added Figure 5; Renumbered Sequentially .................................. 9

Deleted ESD Ratings Parameter, Table 6 ..................................... 10

Changes to Thermal Resistance Section ...................................... 10

Change to V

LOGIC

Pin Description, Table 8 .................................. 11

Change to V

LOGIC

Pin Description, Table 9 .................................. 12

Changes to Figure 21 ...................................................................... 15

Changes to Table 10 ........................................................................ 22

Deleted Endnote 1, Table 11.......................................................... 22

Changes to Update DAC Register with Contents of Input Register n

Section and Write to and Update DAC Channel n (Independent

of LDAC) Section ........................................................................... 23

Changes to Readback Operation Section and Power-Down

Operation Section........................................................................... 24

Changes to Hardware Reset (RESET) Section ............................ 26

Added Software Reset Section ...................................................... 26

Updated Outline Dimensions ....................................................... 29

10/2015—Rev. A to Rev. B

Added 20-Lead LFCSP ...................................................... Universal

Changes to Features Section, General Description Section,

Table 1, Product Highlights Section, and Figure 1 .......................1

Changes to Table 2.............................................................................3

Deleted Figure 5; Renumbered Sequentially .................................8

Change to Table 5 ..............................................................................8

Added Table 6; Renumbered Sequentially .....................................8

Change to Table 7 ..............................................................................9

Added Figure 6 and Table 8 .......................................................... 10

Change to Figure 10 to Figure 12 ................................................. 11

Change to Figure 13 to Figure 18 ................................................. 12

Changes to Figure 19, Figure 20, and Figure 22 ......................... 13

Rev. D | Page 2 of 30

Data Sheet

Change to Figure 25, Figure 28, and Figure 30 ...........................14

Change to Figure 31, Figure 34, Figure 35, and Figure 36 .........15

Change to Figure 37 and Figure 38 ...............................................16

Changes to Transfer Function Section and Output Amplifiers

Section ..............................................................................................19

Change to Table 9 ............................................................................20

Changes to Write to and Update DAC Channel n (Independent

of LDAC) Section ............................................................................21

Changes to Readback Operation Section .....................................22

Changes to LDAC Mask Register Section and Table 14.............23

Changes to Reset Select Pin (RSTSEL) Section ...........................24

Added Amplifier Gain Selection on LFCSP Section, Table 16,

and Table 17 .....................................................................................24

Added Figure 53, Outline Dimensions.........................................27

Changes to Ordering Guide ...........................................................27

AD5676

2/2015—Rev. 0 to Rev. A

Changes to Table 2 ............................................................................ 3

Change to RESET Pulse Activation Time Parameter, Table 4..... 6

Change to Terminology Section.................................................... 17

Changes to Transfer Function Section and Output Amplifiers

Section .............................................................................................. 19

Changes to Hardware Reset (RESET) Section ............................ 24

Changes to Ordering Guide ........................................................... 27

10/2014—Revision 0: Initial Version

Rev. D | Page 3 of 30

AD5676

SPECIFICATIONS

Data Sheet

= 2.7 V to 5.5 V, 1.62 V ≤ V

LOGIC

≤ 5.5 V, resistive load (R

) = 2 kΩ, capacitive load (C

) = 200 pF, all specifications −40°C to +125°C,

unless otherwise noted.

Table 2.

Parameter

STATIC PERFORMANCE

Resolution

Relative Accuracy (INL)

Differential Nonlinearity

(DNL)

Zero Code Error

Offset Error

Full-Scale Error

Min

A Grade

Typ

Max

Min

B Grade

Typ

Max

Unit

Bits

LSB

% of full-

scale range

(FSR)

% of FSR

µV/°C

mV/V

µV

µV/mA

µV

Test Conditions/Comments

±1.8

±1.7

±0.7

±0.5

0.8

−0.75

−0.1

−0.018

−0.013

+0.04

−0.02

+0.03

+0.006

±1

0.25

±2

±3

±2

±8

±1

±6

±4

±0.28

±0.14

±0.24

±0.12

±0.3

±0.25

±1.8

±1.7

±0.7

±0.5

0.8

−0.75

−0.1

−0.018

−0.013

+0.04

−0.02

+0.03

+0.006

±1

0.25

±2

±3

±2

±3

±1

1.6

±2

±1.5

±0.14

±0.07

±0.12

±0.06

±0.18

±0.14

Gain = 1

Gain = 2

Gain = 1

Gain = 2

Gain = 1 or gain = 2

Gain = 1

Gain = 2

Gain = 1

Gain = 2

Gain = 1

Gain = 2

Gain = 1

Gain = 2

DAC code = midscale, V

= 5 V

± 10%

Due to single channel, full-

scale output change

Due to load current change

Due to powering down (per

channel)

Gain = 1

Gain = 2

= ∞

= 1 kΩ

5 V ± 10%, DAC code = midscale,

−30 mA ≤ I

OUT

≤ +30 mA

3 V ± 10%, DAC code = midscale,

−20 mA ≤ I

OUT

≤ +20 mA

Gain Error

Total Unadjusted Error (TUE)

Offset Error Drift

DC Power Supply Rejection

Ratio (PSRR)

DC Crosstalk

OUTPUT CHARACTERISTICS

Output Voltage Range

Output Current Drive (I

OUT

)

Capacitive Load Stability

Resistive Load

Load Regulation

183

177

REF

2 × V

REF

183

177

2.5

REF

2 × V

REF

kΩ

µV/mA

Ω

µs

Short-Circuit Current

Load Impedance at Rails

Power-Up Time

REFERENCE INPUT

Reference Input Current

Reference Input Range

Reference Input Impedance

2.5

Exiting power-down mode,

= 5 V

REF

= V

LOGIC

= 5.5 V, gain = 1

REF

= V

LOGIC

= 5.5 V, gain = 2

Gain = 1

Gain = 2

Gain = 1

Gain = 2

398

789

398

789

Rev. D | Page 4 of 30

µA

kΩ

Data Sheet

Parameter

LOGIC INPUTS

Input Current

Input Voltage

Low, V

High, V

Pin Capacitance

LOGIC OUTPUTS (SDO)

Output Voltage

Low, V

High, V

Floating State Output

Capacitance

POWER REQUIREMENTS

LOGIC

Supply Current (I

LOGIC

)

Min

A Grade

Typ

Max

±1

0.3 ×

LOGIC

0.7 ×

LOGIC

0.7 ×

LOGIC

Min

B Grade

Typ

Max

±1

0.3 ×

LOGIC

Unit

µA

AD5676

Test Conditions/Comments

Per pin

0.4

LOGIC

−

0.4

LOGIC

−

0.4

SINK

= 200 μA

SOURCE

= 200 μA

1.62

2.7

REF

1.5

1.1

5.5

1.62

2.7

REF

1.5

1.1

5.5

µA

Power-on, −40°C to +105°C

Power-on, −40°C to +125°C

Power-down, −40°C to +105°C

Power-down, −40°C to +125°C

Gain = 1

Gain = 2

Supply Current (I

)

Normal Mode

All Power-Down Modes

1.26

1.3

1.7

2.5

5.5

1.26

1.3

1.7

2.5

5.5

µA

−40°C to +85°C

−40°C to +105°C

Three-state, −40°C to +85°C

Power-down to 1 kΩ, −40°C to

+85°C

Three-state, −40°C to +105°C

Power-down to 1 kΩ, −40°C to

+105°C

Three-state, −40°C to +125°C

Power-down to 1 kΩ, −40°C to

+125°C

DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when V

REF

= V

with gain = 1 or when V

REF

/2 =

with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.

See the Terminology section.

Channel 0, Channel 1, Channel 2, and Channel 3 can together source/sink 40 mA. Similarly, Channel 4, Channel 5, Channel 6, and Channel 7 can together source/sink

40 mA up to a junction temperature of 125°C.

= 5 V. The

AD5676

includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum operation junction temperature can impair device reliability.

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.

Interface inactive. All DACs active. DAC outputs unloaded.

All DACs powered down.

Rev. D | Page 5 of 30