a
FEATURES
Guaranteed 16-Bit Monotonicity
Monolithic BiMOS II Construction
0.01% Typical Nonlinearity
8- and 16-Bit Bus Compatibility
3 s Settling to 16 Bits
Low Drift
Low Power
Low Noise
APPLICATIONS
Robotics
Closed-Loop Positioning
High-Resolution ADCs
Microprocessor-Based Process Control
MIL-STD-883 Compliant Versions Available
16-Bit Monotonic
Voltage Output D/A Converter
AD569
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD569 is a monolithic 16-bit digital-to-analog converter
(DAC) manufactured in Analog Devices’ BiMOS II process.
BiMOS II allows the fabrication of low power CMOS logic
functions on the same chip as high precision bipolar linear cir-
cuitry. The AD569 chip includes two resistor strings, selector
switches decoding logic, buffer amplifiers, and double-buffered
input latches.
The AD569’s voltage-segmented architecture insures 16-bit
monotonicity over time and temperature. Integral nonlinearity is
maintained at
±
0.01%, while differential nonlinearity is
±
0.0004%. The on-chip, high-speed buffer amplifiers provide a
voltage output settling time of 3
µs
to within
±
0.001% for a
full-scale step.
The reference input voltage which determines the output range
can be either unipolar or bipolar. Nominal reference range is
±
5 V and separate reference force and sense connections are
provided for high accuracy applications. The AD569 can oper-
ate with an ac reference in multiplying applications.
Data may be loaded into the AD569’s input latches from 8- and
16-bit buses. The double-buffered structure simplifies 8-bit bus
interfacing and allows multiple DACs to be loaded asynchro-
nously and updated simultaneously. Four TTL/LSTTL/5 V
CMOS-compatible signals control the latches:
CS, LBE, HBE,
and
LDAC
The AD569 is available in five grades: J and K versions are
specified from 0°C to +70°C and are packaged in a 28-pin plas-
tic DIP and 28-pin PLCC package; AD and BD versions are
specified from –25°C to +85°C and are packaged in a 28-pin
ceramic DIP. The SD version, also in a 28-pin ceramic DIP, is
specified from –55°C to +125°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Monotonicity to 16 bits is insured by the AD569’s voltage-
segmented architecture.
2. The output range is ratiometric to an external reference or ac
signal. Gain error and gain drift of the AD569 are negligible.
3. The AD569’s versatile data input structure allows loading
from 8- and 16-bit buses.
4. The on-chip output buffer amplifier can supply
±
5 V into a
1 kΩ load, and can drive capacitive loads of up to 1000 pF.
5. Kelvin connections to the reference inputs preserve the gain
and offset accuracy of the transfer function in the presence of
wiring resistances and ground currents.
6. The AD569 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Data-
book or current AD569/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD569* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DISCUSSIONS
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DOCUMENTATION
Data Sheet
•
AD569: 16-Bit Monotonic Voltage Output D/A Converter
Data Sheet
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•
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DESIGN RESOURCES
•
AD569 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
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AD569–SPECIFICATIONS
Model
Parameter
RESOLUTION
LOGIC INPUTS
V
IH
(Logic “l”)
V
IL
(Logic “0”)
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0 V)
TRANSFER FUNCTION
CHARACTERISTICS
Integral Nonlinearity
T
MIN
to T
MAX
Differential Nonlinearity
T
MIN
to T
MAX
Unipolar Offset
2
T
MIN
to T
MAX
Bipolar Offset
2
T
MIN
to T
MAX
Full Scale Error
2
T
MIN
to T
MAX
Bipolar Zero
2
T
MIN
to T
MAX
REFERENCE INPUT
+V
REF
Range
3
–V
REF
Range
Resistance
OUTPUT CHARACTERISTICS
Voltage
Capacitive Load
Resistive Load
Short Circuit Current
POWER SUPPLIES
Voltage
+V
S
–V
S
Current
+I
S
–I
S
Power Supply Sensitivity
5
+10.8 V
≤
+V
S
≤
+13.2 V
–10.8 V
≥
–V
S
≥
–13.2 V
TEMPERATURE RANGE
Specified
JN, KN, JP, KP
AD, BD
SD
Storage
JN, KN, JP, KP
AD, BD, SD
–5
–5
15
–5
1
10
Min
2.0
0
(T
A
= +25 C, +V
S
= +12 V, –V
S
= –12 V, +V
REF
= +5 V, –V
REF
= –5 V, unless
otherwise noted.)
AD569KN/KP/BD
Min
Typ
Max
16
2.0
0
5.5
0.8
10
10
2.0
0
Min
AD569SD
Typ
Max
16
5.5
0.8
10
10
Units
Bits
Volts
Volts
µA
µA
AD569JN/JP/AD
Typ
Max
16
5.5
0.8
10
10
±
0.02
±
0.02
±
1/2
±
1/2
0.04
0.04
1
1
500
750
500
750
350
750
0.04
0.04
+5
+5
25
+5
1000
–5
–5
15
–5
1
±
0.01
±
0.020
±
1/4
±
1/2
0.024
0.024
1/2
1
350
450
350
450
350
750
0.024
0.024
+5
+5
25
+5
1000
–5
–5
15
–5
1
10
0.04
0.04
1
1
500
750
500
750
350
750
0.04
0.04
+5
+5
25
+5
1000
% FSR
1
% FSR
LSB
LSB
µV
µV
µV
µV
µV
µV
% FSR
% FSR
Volts
Volts
kΩ
4
Volts
pF
kΩ
mA
20
20
20
10
+10.8
–10.8
+12
–12
+9
–9
±
0.5
±
1
+13.2
–13.2
+13
–13
2
3
+10.8
–10.8
+12
–12
+9
–9
±
0.5
±
1
+13.2
–13.2
+13
–13
2
3
+10.8
–10.8
+12
–12
+9
–9
±
0.5
±
1
+13.2
–13.2
+13
–13
2
3
Volts
Volts
mA
mA
ppm/%
ppm/%
0
–25
–65
–65
+70
+85
+150
+150
0
–25
–65
–65
+70
+85
–55
+150
+150
+125
°C
°C
°C
°C
°C
–65
+150
NOTES
1
FSR stands for Full-Scale Range, and is 10 V for a –5 V to +5 V span.
2
Refer to Definitions section.
3
For operation with supplies other than
±
12 V, refer to the Power Supply and Reference Voltage Range Section.
4
Measured between +V
REF
Force and –V
REF
Force.
5
Sensitivity of Full-Scale Error due to changes in +V
S
and sensitivity of Offset to changes in –V
S
.
Specifications subject to change without notice.
Specifications shown in
boldface
are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
–2–
REV. A
AD569
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance Only and are not subject to test.
+V
S
= +12 V; –V
S
= –12 V; +V
REF
= +5 V; –V
REF
= –5 V excepts where stated.
Parameter
Output Voltage Settling
(Time to
±
0.001% FS
For FS Step)
Digital-to-Analog Glitch
Impulse
Multiplying Feedthrough
Output Noise Voltage
Density (1 kHz-1 MHz)
Limit
5
3
6
4
500
Units
µs
max
µs
typ
µs
max
µs
typ
nV-sec typ
Test Conditions/Comments
No Load Applied
(DAC output measured from falling edge of
LDAC.)
V
OUT
Load = 1 kΩ, C
LOAD
= 1000 pF.
(DAC output measured from falling edge of
LDAC.
)
Measured with V
REF
= 0 V. DAC registers alternatively loaded
with input codes of 8000
H
and 0FFF
H
(worst-case
transition). Load = 1 kΩ.
+V
REF
= 1 V rms 10 kHz sine wave,
–V
REF
= 0 V
Measured between V
OUT
and –V
REF
–100
40
dB max
nV/
Hz
typ
TIMING CHARACTERISTICS
Parameter
Case A
t
WC
t
SC
t
HC
Case B
t
WB
t
SB
t
HB
t
SCS
t
HCS
t
WD
Case C
t
WB
t
SB
t
HB
t
SCS
t
HCS
120
60
20
70
80
20
120
10
120
120
80
20
120
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Limit
Units
(+V
S
= +12 V, –V
S
= –12 V, V
IH
= 2.4 V, V
IL
= 0.4 V,T
MIN
to T
MAX
)
Test Conditions/Comments
150 ns Pulse on
HBE, LBE,
and
LDAC
T
HS
= 140 ns min, T
HH
= 10 ns min
CS
Pulse Width
CS
Data Setup Time
CS
Data Hold Time
None
HBE, LBE
Pulse Width
HBE, LBE
Data Setup Time
HBE, LBE
Data Hold Time
CS
Setup Time
CS
Hold Time
LDAC
Pulse Width
None
Figure 2a. AD569 Timing Diagram – Case B
HBE, LBE
Pulse Width
HBE, LBE
Data Setup Time
HBE, LBE
Data Hold Time
CS
Setup Time
CS
Hold Time
Figure 1. AD569 Timing Diagram – Case A
Figure 2b. AD569 Timing Diagram – Case C
REV. A
–3–
AD569
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
+V
S
(Pin 1) to GND (Pin 18) . . . . . . . . . . . . . . +18 V, –0.3 V
–V
S
(Pin 28) to GND (Pin 18) . . . . . . . . . . . . . . –18 V, +0.3 V
+V
S
(Pin 1) to –V
S
(Pin 28) . . . . . . . . . . . . . . . +26.4 V, –0.3 V
Digital Inputs
(Pins 4-14, 19-27) to GND (Pin 18) . . . . . . . . . +V
S
, –0.3 V
+V
REF
Force (Pin 3) to +V
REF
Sense (Pin 2) . . . . . . . .
±
16.5 V
–V
REF
Force (Pin 15) to –V
REF
Sense (Pin 16) . . . . . . .
±
16.5 V
V
REF
Force (Pins 3, 15) to GND (Pin 18) . . . . . . . . . . . . .
±
V
S
V
REF
Sense (Pins 2, 16) to GND (Pin 18) . . . . . . . . . . . . .
±
V
S
V
OUT
(Pin 17) . . . . . . . . . . . . . . . . . . Indefinite Short to GND
. . . . . . . . . . . . . . . . . . . . . . . .
Momentary Short to +V
S,
–V
S
Power Dissipation (Any Package) . . . . . . . . . . . . . . . 1000 mW
Operating Temperature Range
Commercial Plastic (JN, KN, JP, KP Versions) 0°C to +70°C
Industrial Ceramic (AD, BD Versions) . . . . –25°C to +85°C
Extended Ceramic (SD Versions) . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 10 secs) . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The AD569 features input protection circuitry consisting of large “distributed” diodes and polysilicon
series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy
pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD569 has been
classified as a Category A device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment
and discharge without detection. Unused devices must be stored in conductive foam or shunts, and
the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
WARNING!
ESD SENSITIVE DEVICE
PIN DESIGNATIONS
ORDERING GUIDE
Model
1
Integral Nonlinearity
+25 C
T
MIN
–T
MAX
±
0.04%
±
0.04%
±
0.024%
±
0.024%
±
0.04%
±
0.024%
±
0.04%
±
0.04%
±
0.04%
±
0.024%
±
0.024%
±
0.04%
±
0.024%
±
0.04%
Differential Nonlinearity
+25 C
T
MIN
–T
MAX
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
±
1 LSB
Temperature
Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
Package
Option
2
N-28
P-28A
N-28
P-28A
D-28
D-28
D-28
AD569JN
AD569JP
AD569KN
AD569KP
AD569AD
AD569BD
AD569SD
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook
or current AD569/883B data sheet.
2
D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
–4–
REV. A
