Industrial Current Out Driver, Single-Supply,
55 V Maximum Supply, Programmable Ranges
Data Sheet
FEATURES
Current output ranges: 0 mA to 24 mA or 4 mA to 20 mA
±0.03% FSR typical total unadjusted error (TUE)
±5 ppm/°C typical output drift
2% overrange
Flexible serial digital interface
On-chip output fault detection
PEC error checking
Asynchronous CLEAR function
Power supply range
AV
DD
: 12 V (± 10%) to 55 V (maximum)
Output loop compliance to AV
DD
− 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
CLEAR
CLRSEL
SCLK/OUTEN*
SDIN/R0*
SYNC/RSET*
SDO
HW SELECT
VIN
VREF
RESET
IOUT RANGE
SCALING
IOUT
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
STATUS
REGISTER
DVCC GND
AVDD GND
AD5749
FUNCTIONAL BLOCK DIAGRAM
AD5749
AVDD
R2
R3
APPLICATIONS
Process control
Actuator control
PLCs
FAULT/TEMP*
NC/IFAULT*
OVERTEMP
IOUT OPEN FAULT
IOUT OPEN FAULT
POWER-
ON RESET
AD2/R1*
AD1/R2*
R
SET
REXT1
REXT2
IOUT
OPEN FAULT
AD0/R3*
08923-001
* DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT,
HARDWARE MODE DENOTED BY
ITALIC
TEXT. FOR EXAMPLE, FOR
FAULT/TEMP PIN, IN SOFTWARE MODE, THIS PIN TAKES ON FAULT
FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON
TEMP
FUNCTION.
Figure 1.
GENERAL DESCRIPTION
The
AD5749
is a single channel, low cost, precision, current output
driver with hardware or software programmable output ranges.
The software ranges are configured via an SPI-/MICROWIRE™-
compatible serial interface. The
AD5749
targets applications in
PLC and industrial process control. The analog input to the
AD5749
is provided from a low voltage, single-supply digital-to-
analog converter (DAC) and is internally conditioned to provide
the desired output current/voltage range.
The output current range is programmable across two current
ranges: 0 mA to 24 mA, or 4 mA to 20 mA. Current output is
open-circuit protected and can drive inductive loads of 0.1 H.
The device is specified to operate with a power supply range
from 10.8 V to 55 V. Output loop compliance is 0 V to AV
DD
−
2.75 V.
The flexible serial interface is SPI and MICROWIRE compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications. The interface also
features an optional PEC error checking feature using CRC-8
error checking, useful in industrial environments where data
communication corruption can occur.
The device also includes a power-on reset function ensuring
that the device powers up in a known state and an asynchron-
ous CLEAR pin that sets the outputs to the low end of the
selected current range.
An HW SELECT pin is used to configure the part for hardware
or software mode on power-up.
Table 1. Related Devices
Part No.
AD5750
AD5751
AD5748
AD5410/
AD5420
AD5412/
AD5422
Description
Industrial current/voltage output (I/V) driver with
programmable ranges
Industrial I/V output driver, single-supply, 55 V maximum
supply, programmable ranges
Industrial I/V output driver with programmable ranges
Single-channel, 12-/16-bit, serial input, current source
output DAC
Single-channel, 12-/16-bit, serial input, I/V output DAC
Rev. D
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AD5749
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Software Mode ............................................................................ 16
Current Output Architecture .................................................... 18
Driving Inductive Loads ............................................................ 18
Power-On State of the AD5749 ................................................ 18
Default Registers at Power-On ................................................. 18
Reset Function ............................................................................ 18
Data Sheet
OUTEN........................................................................................ 18
Software Control ........................................................................ 18
Hardware Control ...................................................................... 21
Transfer Function ....................................................................... 21
Detailed Description of Features .................................................. 22
Output Fault Alert—Software Mode ....................................... 22
Output Fault Alert—Hardware Mode ..................................... 22
Asynchronous Clear (CLEAR) ................................................. 22
External Current Setting Resistor ............................................ 22
Programmable Overrange Modes ............................................ 22
Packet Error Checking ............................................................... 23
Applications Information .............................................................. 24
Transient Voltage Protection .................................................... 24
Thermal Considerations............................................................ 24
Layout Guidelines....................................................................... 25
Galvanically Isolated Interface ................................................. 25
Microprocessor Interfacing ....................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
1/2018—Rev. C to Rev. D
Changed CP-32-7 to CP-32-2 ...................................... Throughout
Changes to Figure 1 .......................................................................... 1
Changed FAULT, IFAULT, TEMP, VFAULT Parameter to
FAULT, IFAULT, TEMP Parameter; Table 2 ................................. 4
Changes to Figure 4 and Table 5 ..................................................... 8
Updates Outline Dimensions ........................................................ 26
Changes to Ordering Guide .......................................................... 26
3/2017—Rev. B to Rev. C
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 4 .......................................................................... 8
Changes to Theory of Operation Section .................................... 16
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
10/2013—Rev. A to Rev. B
Changes to Table 4.............................................................................7
Changes to Thermal Considerations Section and Table 12 ...... 24
Updated Outline Dimensions ....................................................... 26
7/2012—Rev. 0 to Rev. A
Changes to Figure 3 ...........................................................................6
Changes to Status Bit Read Operation Section........................... 21
Updated Outline Dimensions ....................................................... 26
7/2010—Revision 0: Initial Version
Rev. D | Page 2 of 28
Data Sheet
SPECIFICATIONS
AV
DD
= 12 V (± 10%) to 55 V (maximum), DV
CC
= 2.7 V to 5.5 V, GND = 0 V. R
LOAD
= 300 Ω. All specifications T
MIN
to T
MAX
,
unless otherwise noted.
Table 2.
Parameter
1
INPUT VOLTAGE RANGE
Input Leakage Current
REFERENCE INPUT
Reference Input Voltage
Input Leakage Current
CURRENT OUTPUT
Output Current Ranges
Output Current Overranges
2
ACCURACY (INTERNAL R
SET
)
Total Unadjusted Error (TUE)
A Version
2
Relative Accuracy (INL)
Offset Error
Offset Error TC
Dead Band on Output, RTI
Gain Error
Gain TC
2
Full-Scale Error
Full-Scale TC
ACCURACY (EXTERNAL R
SET
)
Total Unadjusted Error (TUE)
A Version
2
Relative Accuracy (INL)
Offset Error
Offset Error TC
Dead Band on Output, RTI
Gain Error
Gain TC
Full-Scale Error
Full-Scale TC
2
2
2
2
2
AD5749
Min
−1
Typ
0 to 4.096
Max
+1
Unit
V
µA
V
Test Conditions/Comments
Output unloaded
4.096
−1
0
4
0
3.92
+1
24
20
24.5
20.4
External reference must be exactly as stated;
otherwise, accuracy errors show up as error in output
µA
mA
mA
mA
mA
See
Detailed Description of Features
section
See
Detailed Description of Features
section
−0.5
−0.3
−0.02
−16
−10
±0.15
±0.01
+5
±3
8
±0.02
±10
±0.02
±4
+0.5
+0.3
+0.02
+16
+10
14
+0.2
+0.125
+0.2
+0.125
−0.2
−0.125
−0.2
−0.125
% FSR
% FSR
% FSR
µA
µA
ppm FSR/°C
mV
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
T
A
= 25°C
T
A
= 25°C
Referred to 4.096 V input range
T
A
= 25°C
T
A
= 25°C
−0.3
−0.1
−0.02
−14
−11
±0.02
±0.01
+5
±2
8
±0.02
±1
±0.02
±2
+0.3
+0.1
+0.02
+14
+11
+14
+0.08
+0.07
+0.1
+0.07
% FSR
% FSR
% FSR
µA
ppm FSR/°C
mV
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
T
A
= 25°C
T
A
= 25°C
Referred to 4.096 V input range
T
A
= 25°C
−0.08
−0.07
−0.1
−0.07
T
A
= 25°C
Rev. D | Page 3 of 28
AD5749
Parameter
1
OUTPUT CHARACTERISTICS
2
Current Loop Compliance
Voltage
Resistive Load
Inductive Load
Settling Time
4 mA to 20 mA, Full-Scale
Step
120 µA Step, 4 mA to
20 mA Range
DC PSRR
Output Impedance
DIGITAL INPUTS
2
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current
Pin Capacitance
DIGITAL OUTPUTS
2
FAULT, IFAULT, TEMP
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
SDO
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
High Impedance Output
Capacitance
High Impedance Leakage
Current
POWER REQUIREMENTS
AV
DD
DV
CC
Input Voltage
AI
DD
Min
0
Typ
Max
AV
DD
− 2.75
Unit
V
Test Conditions/Comments
Data Sheet
See the Test Conditions/
Comments column
8.5
1.2
1
130
2
−1
5
0.8
+1
H
Chosen such that compliance is not exceeded
Needs appropriate capacitor at higher inductance
values; see the
Driving Inductive Loads
section
250 Ω load
250 Ω load
µs
µs
µA/V
MΩ
JEDEC compliant
V
V
µA
pF
Per pin
Per pin
0.4
0.6
3.6
0.5
DV
CC
− 0.5
0.5
DV
CC
− 0.5
3
+1
V
V
V
V
V
pF
µA
10 kΩ pull-up resistor to DVCC
At 2.5 mA
10 kΩ pull-up resistor to DVCC
Sinking 200 µA
Sourcing 200 µA
−1
10.8
2.7
4.4
5.2
0.3
108
55
5.5
5.6
6.2
1
V
V
mA
mA
mA
mW
DI
CC
Power Dissipation
1
2
Output unloaded, output disabled;
R3, R2, R1, R0 = 0000, RSET = 0
Output enabled
V
IH
= DV
CC
, V
IL
= GND
AV
DD
= 24 V, output unloaded
Temperature range: −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization, not production tested.
Rev. D | Page 4 of 28
Data Sheet
TIMING CHARACTERISTICS
AD5749
AV
DD
= 12 V (± 10%) to 55 V (maximum), DV
CC
= 2.7 V to 5.5 V, GND = 0 V. R
LOAD
= 300 Ω. All specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 3.
Parameter
1, 2
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
, t
10
t
11
t
12
t
13
1
2
Limit at T
MIN
, T
MAX
20
8
8
5
10
5
5
5
1.5
5
40
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs max
ns min
ns max
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
16
th
SCLK falling edge to SYNC rising edge (on 24
th
SCLK falling edge if using PEC)
Minimum SYNC high time (write mode)
Data setup time
Data hold time
CLEAR pulse low/high activation time
Minimum SYNC high time (read mode)
SCLK rising edge to SDO valid (SDO C
L
= 15 pF)
RESET pulse low time
Guaranteed by characterization, but not production tested.
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
Rev. D | Page 5 of 28
