1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478
FEATURES
Fast throughput rate: 1 MSPS
Specified for V
DD
of 2.35 V to 5.25 V
Low power
3.6 mW at 1 MSPS with 3 V supplies
15 mW at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Standby mode: 1 μA maximum
6-lead SOT-23 package
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN
12-/10-/8-BIT
SUCCESSIVE-
APPROXIMATION
ADC
SCLK
CONTROL
LOGIC
SDATA
CS
AD7476/AD7477/AD7478
GND
01024-001
Figure 1.
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The AD7476/AD7477/AD7478
1
are, respectively, 12-bit, 10-bit,
and 8-bit, high speed, low power, successive approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. Each part
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 6 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is initiated at this
point. There are no pipeline delays associated with these parts.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the parts is taken internally from V
DD
. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the parts are 0 V to V
DD
. The conversion
rate is determined by the SCLK.
1
PRODUCT HIGHLIGHTS
1.
2.
3.
First 12-/10-/8-Bit ADCs in SOT-23 Packages.
High Throughput with Low Power Consumption.
Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced while not converting. The parts also feature a
shutdown mode to maximize power efficiency at lower
throughput rates. Current consumption is 1 μA maximum
when in shutdown mode.
Reference Derived from the Power Supply.
No Pipeline Delay. The parts feature a standard successive-
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
4.
5.
Protected by U.S. Patent No. 6,681,332.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
AD7476/AD7477/AD7478
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7476 Specifications ................................................................. 3
AD7477 Specifications ................................................................. 5
AD7478 Specifications ................................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information.................................................................... 13
Converter Operation.................................................................. 13
ADC Transfer Function ............................................................. 13
Typical Connection Diagram ................................................... 14
Modes of Operation ................................................................... 15
Power vs. Throughput Rate ....................................................... 17
Serial Interface ............................................................................ 18
Microprocessor Interfacing ....................................................... 19
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
1/09—Rev. E to Rev. F
Changes to Features.......................................................................... 1
Changes to Ordering Guide .......................................................... 22
4/06—Rev. D to Rev. E
Updated Format .................................................................. Universal
Changes to Table 1 Endnotes .......................................................... 3
Changes to Table 2 Endnotes .......................................................... 5
Changes to Table 3 Endnotes .......................................................... 7
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 22
3/04—Rev. C to Rev. D
Added U.S. Patent Number ..............................................................1
Changes to Specifications .................................................................2
Changes to Absolute Maximum Ratings ........................................6
Changes to AD7476/AD7477/AD7478 to ADSP-21xx
Interface section.............................................................................. 16
2/03—Rev. B to Rev. C
Changes to General Description .....................................................1
Changes to Specifications .................................................................2
Changes to Absolute Maximum Ratings ........................................6
Changes to Ordering Guide .............................................................6
Changes to Typical Connection Diagram section ..................... 10
Changes to Figure 8 caption.......................................................... 11
Changes to Figure 19...................................................................... 16
Changes to Figure 20...................................................................... 17
Updated Outline Dimensions ....................................................... 18
Rev. F | Page 2 of 24
AD7476/AD7477/AD7478
SPECIFICATIONS
AD7476 SPECIFICATIONS
A version: V
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, f
SAMPLE
= 1 MSPS, unless otherwise noted; S and B versions: V
DD
= 2.35 V to 5.25 V,
f
SCLK
= 12 MHz, f
SAMPLE
= 600 kSPS, unless otherwise noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
3
A Version
1,2
69
70
70
−80
−82
−78
−78
10
30
6.5
B Version
1,2
70
71.5
71
72.5
−78
−80
−78
−78
10
30
6.5
S Version
1,2
69
70
70
−78
−80
−78
−78
10
30
6.5
Unit
dB min
dB min
dB typ
dB min
dB typ
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Test Conditions/Comments
f
IN
= 100 kHz sine wave
B version, V
DD
= 2.4 V to 5.25 V
T
A
= 25°C
B version, V
DD
= 2.4 V to 5.25 V
Signal-to-Noise Ratio (SNR)
3
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise (SFDR)
3
Intermodulation Distortion (IMD)
3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
3
Differential Nonlinearity
Offset Error
Gain Error
3
3
3
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
S, B versions, V
DD
= (2.35 V to 3.6 V)
4
;
A version, V
DD
= (2.7 V to 3.6 V)
12
±1
±0.75
±0.5
12
±1.5
±0.6
−0.9/+1.5
±0.75
±1.5
±1.5
12
±1.5
±0.6
−0.9/+1.5
±0.75
±2
±2
±0.5
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUT
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Capacitance, C
IN 5
LOGIC OUTPUT
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
0 to V
DD
±1
30
2.4
1.8
0.4
0.8
±1
±1
10
V
DD
− 0.2
0.4
±10
10
0 to V
DD
±1
30
2.4
1.8
0.4
0.8
±1
±1
10
0 to V
DD
±1
30
2.4
1.8
0.4
0.8
±1
±1
10
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
V
μA max
pF typ
V min
V min
V max
V max
μA max
μA typ
pF max
V min
V max
μA max
pF max
Guaranteed no missed codes to 12 bits
V
DD
= 2.35 V
V
DD
= 3 V
V
DD
= 5 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
− 0.2
V
DD
− 0.2
0.4
0.4
±10
±10
10
10
Straight (Natural) Binary
I
SOURCE
= 200 μA; V
DD
= 2.35 V to 5.25 V
I
SINK
= 200 μA
Rev. F | Page 3 of 24
AD7476/AD7477/AD7478
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
A Version
1,2
0.8
500
350
1000
2.35/5.25
2
1
3.5
1.6
Full Power-Down Mode
Power Dissipation
7
Normal Mode (Operational)
Full Power-Down
1
80
17.5
4.8
5
3
B Version
1,2
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
S Version
1,2
1.33
500
400
600
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
Unit
μs max
ns max
ns max
kSPS max
V min/max
mA typ
mA typ
mA max
mA max
μA max
μA max
mW max
mW max
μW max
μW max
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V, SCLK on or off
V
DD
= 2.35 V to 3.6 V, SCLK on or off
V
DD
= 4.75 V to 5.25 V,
f
SAMPLE
= f
SAMPLE
MAX
6
V
DD
= 2.35 V to 3.6 V,
f
SAMPLE
= f
SAMPLE
MAX
6
SCLK off
SCLK on
V
DD
= 5 V, f
SAMPLE
= f
SAMPLE
MAX
6
V
DD
= 3 V, f
SAMPLE
= f
SAMPLE
MAX
6
V
DD
= 5 V, SCLK off
V
DD
= 3 V, SCLK off
Test Conditions/Comments
16 SCLK cycles
Full-scale step input
Sine wave input ≤ 100 kHz
See Serial Interface section
1
2
Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C.
Operational from V
DD
= 2.0 V.
3
See the Terminology section.
4
Maximum B and S version specifications apply as typical figures when V
DD
= 5.25 V.
5
Guaranteed by characterization.
6
For A version: f
SAMPLE
MAX = 1 MSPS; B and S versions: f
SAMPLE
MAX = 600 kSPS.
7
See the Power vs. Throughput Rate section.
Rev. F | Page 4 of 24
AD7476/AD7477/AD7478
AD7477 SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise (SFDR)
3
Intermodulation Distortion (IMD)
3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
3
Differential Nonlinearity
3
Offset Error
3
Gain Error
3
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Capacitance, C
IN 4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
A Version
1,2
61
−73
−74
−78
−78
10
30
6.5
10
±1
±0.9
±1
±1
0 to V
DD
±1
30
2.4
0.8
0.4
±1
±1
10
S Version
1,2
61
−73
−74
−78
−78
10
30
6.5
10
±1
±0.9
±1
±1
0 to V
DD
±1
30
2.4
0.8
0.4
±1
±1
10
Unit
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
μA max
pF typ
V min
V max
V max
μA max
μA typ
pF max
V min
V max
μA max
pF max
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
Test Conditions/Comments
f
IN
= 100 kHz sine wave, f
SAMPLE
= 1 MSPS
@ 3 dB
Guaranteed no missed codes to 10 bits
V
DD
= 5 V
V
DD
= 3 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
– 0.2
V
DD
– 0.2
0.4
0.4
±10
±10
10
10
Straight (Natural) Binary
800
400
1
800
400
1
I
SOURCE
= 200 μA, V
DD
= 2.7 V to 5.25 V
I
SINK
= 200 μA
ns max
ns max
MSPS max
16 SCLK cycles with SCLK at 20 MHz
See Serial Interface section
Rev. F | Page 5 of 24
