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CMOS Low Cost,
10-Bit Multiplying DAC
AD7533
FEATURES
Low cost 10-bit DAC
Low cost AD7520 replacement
Linearity: ½ LSB, 1 LSB, or 2 LSB
Low power dissipation
Full 4-quadrant multiplying DAC
CMOS/TTL direct interface
Latch free (protection Schottky not required)
Endpoint linearity
GENERAL DESCRIPTION
The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC
manufactured using an advanced thin-film-on-monolithic-
CMOS wafer fabrication process.
Pin and function equivalent to the AD7520 industry standard,
the AD7533 is recommended as a lower cost alternative for old
AD7520 sockets or new 10-bit DAC designs.
AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on 5 V to 15 V power, and
provide proper binary scaling for reference inputs of either
positive or negative polarity.
APPLICATIONS
Digitally controlled attenuators
Programmable gain amplifiers
Function generation
Linear automatic gain controls
FUNCTIONAL BLOCK DIAGRAM
V
REF
20kΩ
S1
10kΩ
20kΩ
S2
10kΩ
20kΩ
S3
10kΩ
20kΩ
SN
I
OUT
2
I
OUT
1
10kΩ
R
FB
01134-001
20kΩ
BIT 1 (MSB)
BIT 2
BIT 3
BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD7533
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Terminology ...................................................................................... 5
Pin Configurations and Function Descriptions ........................... 6
Circuit Description............................................................................7
General Circuit Information........................................................7
Equivalent Circuit Analysis .........................................................7
Operation............................................................................................8
Unipolar Binary Code ..................................................................8
Bipolar (Offset Binary) Code.......................................................8
Applications........................................................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 12
REVISION HISTORY
3/07—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Figure 13, Figure 14, and Figure 17 ........................... 9
Updated Outline Dimensions ....................................................... 10
Changes to Ordering Guide .......................................................... 12
1/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings ....................................... 4
Added Pin Configurations
and Function Descriptions Section................................................ 6
Updated Outline Dimensions ....................................................... 10
Changes to Ordering Guide .......................................................... 12
3/04—Rev. 0 to Rev. A
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................3
Changes to Ordering Guide .............................................................3
Updated Outline Dimensions..........................................................7
Rev. C | Page 2 of 12
AD7533
SPECIFICATIONS
V
DD
= 15 V, V
OUT
1 = V
OUT
2 = 0 V, V
REF
= 10 V, unless otherwise noted.
Table 1.
Parameter
STATIC ACCURACY
Resolution
Relative Accuracy
1
AD7533JN, AD7533AQ,
AD7533SQ, AD7533JP
AD7533KN, AD7533BQ,
AD7533KP, AD7533TE
AD7533LN, AD7533CQ, AD7533UQ
DNL
Gain Error
2, 3
Supply Rejection
4
∆Gain/∆V
DD
Output Leakage Current
I
OUT
1
I
OUT
2
DYNAMIC ACCURACY
Output Current Settling Time
Feedthrough Error
Propagation Delay
Glitch Impulse
REFERENCE INPUT
Input Resistance (VREF)
ANALOG OUTPUTS
Output Capacitance
C
IOUT1
C
IOUT2
C
IOUT1
C
IOUT2
DIGITAL INPUTS
Input High Voltage (V
INH
)
Input Low Voltage (V
INL
)
Input Leakage Current (I
IN
)
Input Capacitance (C
IN
)
POWER REQUIREMENTS
V
DD
V
DD
Ranges
5
I
DD
T
A
= 25°C
10 Bits
±0.2% FSR maximum
±0.1% FSR maximum
±0.05% FSR maximum
±1 LSB maximum
±1% FS maximum
0.001%/% maximum
±5 nA maximum
±5 nA maximum
600 ns maximum
4
±0.05% FSR maximum
5
100 ns typical
100 nV-s typical
5 kΩ min, 20 kΩ maximum
T
A
= Operating Range
10 Bits
±0.2% FSR maximum
±0.1% FSR maximum
±0.05% FSR maximum
±1 LSB maximum
±1% FS maximum
0.001%/% maximum
±200 nA maximum
±200 nA maximum
800 ns
5
±0.1% FSR maximum
5
100 ns typical
100 nV-s typical
5 kΩ min, 20 kΩ maximum
6
11 kΩ nominal
Test Conditions
Digital input = V
INH
Digital inputs = V
INH
, V
DD
= 14 V to 17 V
Digital inputs = V
INL
, V
REF
= ±10 V
Digital inputs = V
INH
, V
REF
= ±10 V
To 0.05% FSR; R
LOAD
= 100 Ω, digital
inputs = V
INH
to V
INL
or V
INL
to V
INH
Digital inputs = V
INL
, V
REF
= ±10 V,
100 kHz sine wave
50 pF maximum
5
20 pF maximum
5
30 pF maximum
5
50 pF maximum
5
2.4 V minimum
0.8 V maximum
±1 μA maximum
8 pF maximum
5
15 V ± 10%
5 V to 16 V
2 mA maximum
25 μA maximum
100 pF maximum
5
35 pF maximum
5
35 pF maximum
5
100 pF maximum
5
2.4 V minimum
0.8 V maximum
±1 μA maximum
8 pF maximum
5
15 V ± 10%
5 V to 16 V
2 mA maximum
50 μA maximum
Digital inputs = V
INH
Digital inputs = V
INL
V
IN
= 0 V and V
DD
Rated accuracy
Functionality with degraded performance
Digital inputs = V
INL
or V
INH
D
Digital inputs over V
IN
1
2
FSR = full-scale range.
Full scale (FS) = V
REF
.
3
Maximum gain change from T
A
= 25°C to T
MIN
or T
MAX
is ±0.1% FSR.
4
AC parameter, sample tested to ensure specification compliance.
5
Guaranteed, not tested.
6
Absolute temperature coefficient is approximately −300 ppm/°C.
Rev. C | Page 3 of 12
AD7533
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C unless otherwise noted.
Table 2.
Parameter
V
DD
to GND
R
FB
to GND
V
REF
to GND
Digital Input Voltage Range
I
OUT
1, I
OUT
2 to GND
Power Dissipation (Any Package)
To 75°C
Derates above 75°C by
Operating Temperature Range
Plastic (JN, JP, KN, KP, LN Versions)
Hermetic (AQ, BQ, CQ Versions)
Hermetic (SQ, TE, UQ Versions)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V, +17 V
±25 V
±25 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
450 mW
6 mW/°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 4 of 12
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