–4.75/–5.25 –4.75/–5.25 –4.75/–5.25 V min/V max Specified Performance also applies to V
SS
= 0 V
for unipolar ranges.
V
OUT
= V
IN
= 2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V
13
13
13
mA max
Output unloaded
mA max
Outputs unloaded
V
OUT
= V
IN
= –2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V
4
4
4
mA max
Output unloaded
mA max
Outputs unloaded
V
IN
to V
OUT
match with V
IN
=
±
2.5 V,
20 kHz sine wave
1
1
1
1
1
1
1
1
% typ
% typ
NOTES
1
Specifications apply to both DACs in the AD7669. V
OUT
applies to both V
OUT
A and V
OUT
B of the AD7669.
2
Except where noted, specifications apply for all output ranges including bipolar ranges with dual supply operation.
3
Temperature ranges as follows:
J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
4
1 LSB = 4.88 mV for 0 V to +1.25 V output range, 9.76 mV for 0 V to +2.5 V and
±
1.25 V ranges and 19.5 mV for
±
2.5 V range.
5
See Terminology.
6
Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar full-scale voltage is (FS – 1 LSB); ideal bipolar positive full-scale voltage is (FS/2 – 1 LSB)
and ideal bipolar negative full-scale voltage is –FS/2.
7
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
AD7569/AD7669
ADC SPECIFICATIONS
(V
DD
= +5 V 5%; V
SS1
= RANGE = AGND
DAC
= AGND
DAC
= DGND = 0 V; f
CLK
= 5 MHz external unless other-
wise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.) Specifications apply to Mode 1 interface.
AD7569
J, A Versions
3
AD7669
J Version
AD7569
K, B
Versions
Parameter
DC ACCURACY
Resolution
3
Total Unadjusted Error
4
Relative Accuracy
4
Differential Nonlinearity
4
Unipolar Offset Error
@ +25°C
T
MIN
to T
MAX
Bipolar Zero Offset Error
@ +25°C
T
MIN
to T
MAX
Full-Scale Error
5
@ +25°C
T
MIN
to T
MAX
∆Full
Scale/∆V
DD
, T
A
= +25°C
∆Full
Scale/∆V
SS
, T
A
= +25°C
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
4
(SNR)
Total Harmonic Distortion
4
(THD)
Intermodulation Distortion
4
(IMD)
Frequency Response
Track/Hold Acquisition Time
7
ANALOG INPUT
Input Voltage Ranges
Unipolar
Bipolar
Input Current
Input Capacitance
LOGIC INPUTS
CS, RD, ST,
CLK,
RESET,
RANGE
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Capacitance
8
CS, RD, ST,
RANGE,
RESET
Input Leakage Current
CLK
Input Current
I
INL
I
INH
LOGIC OUTPUTS
DB0–DB7,
INT, BUSY
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
DB0–DB7
Floating State Leakage Current
Floating State Output Capacitance
8
Output Coding (Single Supply)
Output Coding (Dual Supply)
CONVERSION TIME
With External Clock
With Internal Clock, T
A
= +25°C
AD7569
S Version
AD7569
T Version
Units
Conditions/Comments
8
±
3
±
1
±
1
±
2
±
3
±
3
±
3.5
–4, +0
–5.5, +1.5
0.5
0.5
44
48
60
0.1
200
8
±
3
±
1/2
±
3/4
±
1.5
±
2.5
±
2.5
±
3
–4, +0
–5.5, +1.5
0.5
0.5
46
48
60
0.1
200
8
±
4
±
1
±
1
±
2
±
3
±
3
±
4
–4, +0
–7.5, +2
0.5
0.5
44
48
60
0.1
300
8
±
4
±
1/2
±
3/4
±
1.5
±
2.5
±
2.5
±
3.5
–4, +0
–7.5, +2
0.5
0.5
45
48
60
0.1
300
Bits
LSB typ
LSB max
LSB max
LSB max
LSB max
No Missing Codes
Typical tempco is 10
µV/°C
for +1.25 V range; V
SS
= 0 V
Typical tempco is 20
µV/°C
for + 1.25 V range; V
SS
= –5 V
LSB max
LSB max
V
DD
= 5 V
LSB max
LSB max
LSB max
LSB max
dB min
dB max
dB typ
dB typ
ns typ
V
IN
= +2.5 V;
∆V
DD
=
±
5%
V
IN
= –2.5 V;
∆V
SS
=
±
5%
V
IN
= 100 kHz full-scale sine wave with f
SAMPLING
= 400 kHz
6
V
IN
= 100 kHz full-scale sine wave with f
SAMPLING
= 400 kHz
6
fa = 99 kHz, fb = 96.7 kHz with f
SAMPLING
= 400 kHz
V
IN
=
±
2.5 V, dc to 200 kHz sine wave
±
300
10
0 to +1.25/ +2.5
±
1.25/± 2.5
±
300
10
±
300
10
±
300
10
Volts
Volts
µA
max
pF typ
V
DD
= +5 V; V
SS
= 0 V
V
DD
= +5 V; V
SS
= –5 V
See equivalent circuit Figure 5
0.8
2.4
10
10
0.8
2.4
10
10
0.8
2.4
10
10
0.8
2.4
10
10
V max
V min
pF max
µA
max
V
IN
= 0 to V
DD
–1.6
40
–1.6
40
–1.6
40
–1.6
40
mA max
µA
max
V
IN
= 0 V
V
IN
= V
DD
0.4
4.0
10
10
0.4
4.0
0.4
4.0
0.4
4.0
10
10
V max
V min
µA
max
pF max
I
SINK
= 1.6 mA
I
SOURCE
= 200
µA
10
10
10
10
Binary
2s Complement
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
µs
max
µs
min
µs
max
f
CLK
= 5 MHz
Using recommended clock components shown in Figure 21.
Clock frequency can be adjusted by varying R
CLK
.
POWER REQUIREMENTS
As per DAC Specifications
NOTES
1
Except where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.
2
Temperature ranges are as follows: J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
3
1 LSB = 4.88 mV for 0 V to +1.25 V range, 9.76 mV for 0 V to +2.5 V and
±
1.25 V ranges and 19.5 mV for +2.5 V range.
4
See Terminology.
5
Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar last code transition occurs at (FS – 3/2 LSB). Ideal bipolar last code transition occurs at
(FS/2 – 3/2 LSB).
6
Exact frequencies are 101 kHz and 384 kHz to avoid harmonics coinciding with sampling frequency.
7
Rising edge of
BUSY
to falling edge of
ST.
The time given refers to the acquisition time, which gives a 3 dB degradation in SNR from the tested figure.
8
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
AD7569/AD7669–TIMING CHARACTERISTICS
1
(See Figures 8, 10, 12; V
Parameter
DAC Timing
t
1
t
2
t
3
t
4
t
5
ADC Timing
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
132
t
143
t
15
t
16
t
172
Limit at
25 C (All Grades)
80
0
0
60
10
50
110
20
0
0
60
0
60
95
10
60
65
120
60
90
Limit at
T
MIN
, T
MAX
(J, K, A, B Grades)
80
0
0
70
10
50
130
30
0
0
75
0
75
120
10
75
75
140
75
115
Limit at
T
MIN
, T
MAX
(S, T Grades)
90
0
0
80
10
50
150
30
0
0
90
0
90
135
10
85
85
160
90
135
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
ns max
DD
=5V
5%; V
SS
= 0 V or –5 V
5%)
Test Conditions/Comments
WR
Pulse Width
CS, A/B
to
WR
Setup Time
CS, A/B
to
WR
Hold Time
Data Valid to
WR
Setup Time
Data Valid to
WR
Hold Time
ST
Pulse Width
ST
to
BUSY
Delay
BUSY
to
INT
Delay
BUSY
to
CS
Delay
CS
to
RD
Setup Time
RD
Pulse Width Determined by t
13
.
CS
to
RD
Hold Time
Data Access Time after
RD;
C
L
= 20 pF
Data Access Time after
RD;
C
L
= 100 pF
Bus Relinquish Time after
RD
RD
to
INT
Delay
RD
to
BUSY
Delay
Data Valid Time after
BUSY;
C
L
= 20 pF
Data Valid Time after
BUSY;
C
L
= 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t
13
and t
17
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3
t
l4
is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
Specifications subject to change without notice.
a. High-Z to V
OH
b. High-Z to V
OL
a. V
OH
to High-Z
b. V
OL
to High-Z
Figure 1. Load Circuits for Data Access Time Test
ABSOLUTE MAXIMUM RATINGS
Figure 2. Load Circuits for Bus Relinquish Time Test
