Change to Functional Block Diagram ........................................... 1
Changes to Specifications Section.................................................. 3
Changes to Specifications Endnote 1............................................. 5
Changes to Table 5, Table 6, and Table 7 ..................................... 11
Changes to Table 8, Table 9, and Table 10 ................................... 12
Changes to Table 16........................................................................ 16
Changes to Overview Section ....................................................... 20
Renamed Applications Section to Applications Information... 29
Changes to Ordering Guide .......................................................... 30
4/05—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings........................................8
Changes to Figure 17.......................................................................22
Changes to Data Output Coding Section.....................................24
Changes to Calibration Section .....................................................26
Changes to Ordering Guide ...........................................................30
10/04—Revision 0: Initial Version
Rev. B | Page 2 of 32
AD7792/AD7793
SPECIFICATIONS
AV
DD
= 2.7 V to 5.25 V; DV
DD
= 2.7 V to 5.25 V; GND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
ADC CHANNEL
Output Update Rate
No Missing Codes
2
Resolution
Output Noise and Update Rates
Integral Nonlinearity
Offset Error
3
Offset Error Drift vs. Temperature
4
Full-Scale Error
3, 5
Gain Drift vs. Temperature
4
Power Supply Rejection
ANALOG INPUTS
Differential Input Voltage Ranges
Absolute AIN Voltage Limits
2
Unbuffered Mode
Buffered Mode
In-Amp Active
Common-Mode Voltage, V
CM
Analog Input Current
Buffered Mode or In-Amp Active
Average Input Current
2
Average Input Current Drift
Unbuffered Mode
Average Input Current
Average Input Current Drift
Normal Mode Rejection
2
Internal Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
External Clock
@ 50 Hz, 60 Hz
@ 50 Hz
@ 60 Hz
Common-Mode Rejection
@ DC
@ 50 Hz, 60 Hz
2
@ 50 Hz, 60 Hz
2
AD7792B/AD7793B
1
4.17 to 470
24
16
Unit
Hz nom
Bits min
Bits min
Test Conditions/Comments
f
ADC
< 242 Hz, AD7793
AD7792
See Output Noise and Resolution Specifications
See Output Noise and Resolution Specifications
±15
±1
±10
±10
±1
±3
100
±V
REF
/Gain
ppm of FSR max
μV typ
nV/°C typ
μV typ
ppm/°C typ
ppm/°C typ
dB min
V nom
Gain = 1 to 16, external reference
Gain = 32 to 128, external reference
AIN = 1 V/gain, gain ≥ 4, external reference
V
REF
= REFIN(+)
−
REFIN(−) or internal reference,
gain = 1 to 128
Gain = 1 or 2
Gain = 1 or 2
Gain = 4 to 128
V
CM
= (AIN(+) + AIN(−))/2, gain = 4 to 128
GND – 30 mV
AV
DD
+ 30 mV
GND + 100 mV
AV
DD
– 100 mV
GND + 300 mV
AV
DD
– 1.1
0.5
V min
V max
V min
V max
V min
V max
V min
±1
±250
±2
±400
±50
nA max
pA max
pA/°C typ
nA/V typ
pA/V/°C typ
Gain = 1 or 2, update rate < 100 Hz
Gain = 4 to 128, update rate < 100 Hz
Gain = 1 or 2.
Input current varies with input voltage
65
80
90
80
94
90
100
100
100
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
dB min
80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
6
100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000
6
90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
6
100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000
6
AIN = 1 V/gain, gain ≥ 4
50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
6
50 ± 1 Hz (FS[3:0] = 1001)
6
, 60 ± 1 Hz
(FS[3:0] = 1000)
6
Rev. B | Page 3 of 32
AD7792/AD7793
Parameter
REFERENCE
Internal Reference
Internal Reference Initial Accuracy
Internal Reference Drift
2
Power Supply Rejection
External Reference
External REFIN Voltage
Reference Voltage Range
2
AD7792B/AD7793B
1
Unit
Test Conditions/Comments
1.17 ± 0.01%
4
15
85
2.5
0.1
AV
DD
GND
−
30 mV
AV
DD
+ 30 mV
400
±0.03
Same as for analog inputs
100
V min/max
ppm/°C typ
ppm/°C max
dB typ
V nom
V min
V max
V min
V max
nA/V typ
nA/V/°C typ
AV
DD
= 4 V, T
A
= 25°C
REFIN = REFIN(+)
−
REFIN(−)
When V
REF
= AV
DD
, the differential input must be
limited to 0.9 × V
REF
/gain if the in-amp is active
Absolute REFIN Voltage Limits
2
Average Reference Input Current
Average Reference Input Current
Drift
Normal Mode Rejection
Common-Mode Rejection
EXCITATION CURRENT SOURCES
(IEXC1 and IEXC2)
Output Current
Initial Tolerance at 25°C
Drift
Current Matching
Drift Matching
Line Regulation (V
DD
)
Load Regulation
Output Compliance
dB typ
10/210/1000
±5
200
±0.5
50
2
0.2
AV
DD
−
0.65
AV
DD
−
1.1
GND
−
30 mV
±2
0.81
AV
DD
/2
See Figure 10
μA nom
% typ
ppm/°C typ
% typ
ppm/°C typ
%/V typ
%/V typ
V max
V max
V min
°C typ
mV/°C typ
V nom
ms/nF typ
Matching between IEXC1 and IEXC2; V
OUT
= 0 V
AV
DD
= 5 V ± 5%
10 μA or 210 μA currents selected
1 mA currents selected
TEMPERATURE SENSOR
Accuracy
Sensitivity
BIAS VOLTAGE GENERATOR
V
BIAS
V
BIAS
Generator Start-Up Time
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency
2
Duty Cycle
External Clock
Frequency
Applies if user calibrates the temperature
sensor
Dependent on the capacitance on the AIN pin
64 ± 3%
50:50
64
kHz min/max
% typ
kHz nom
A 128 kHz external clock can be used if the
divide-by-2 function is used
(Bit CLK1 = CLK0 = 1)
Applies for external 64 kHz clock; a 128 kHz
clock can have a less stringent duty cycle
Duty Cycle
LOGIC INPUTS
CS
2
45:55 to 55:45
% typ
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
0.8
0.4
2.0
V max
V max
V min
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V or 5 V
Rev. B | Page 4 of 32
AD7792/AD7793
Parameter
SCLK, CLK, and DIN (Schmitt-
Triggered Input)
2
V
T
(+)
V
T
(–)
V
T
(+)
−
V
T
(−)
V
T
(+)
V
T
(–)
V
T
(+)
−
V
T
(−)
Input Currents
Input Capacitance
LOGIC OUTPUTS (INCLUDING CLK)
V
OH
, Output High Voltage
2
V
OL
, Output Low Voltage
2
V
OH
, Output High Voltage
2
V
OL
, Output Low Voltage
2
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
SYSTEM CALIBRATION
2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS
7
Power Supply Voltage
AV
DD
to
GND
DV
DD
to
GND
Power Supply Currents
I
DD
Current
AD7792B/AD7793B
1
Unit
Test Conditions/Comments
1.4/2
0.8/1.7
0.1/0.17
0.9/2
0.4/1.35
0.06/0.13
±10
10
DV
DD
−
0.6
0.4
4
0.4
±10
10
Offset binary
+1.05 × FS
−1.05
× FS
0.8 × FS
2.1 × FS
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
μA max
pF typ
V min
V max
V min
V max
μA max
pF typ
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V
DV
DD
= 3 V
V
IN
= DV
DD
or GND
All digital inputs
DV
DD
= 3 V, I
SOURCE
= 100 μA
DV
DD
= 3 V, I
SINK
= 100 μA
DV
DD
= 5 V, I
SOURCE
= 200 μA
DV
DD
= 5 V, I
SINK
= 1.6 mA (DOUT/RDY)/800 μA
(CLK)
V max
V min
V min
V max
2.7/5.25
2.7/5.25
140
185
400
500
V min/max
V min/max
μA max
μA max
μA max
μA max
μA max
110 μA typ @ AV
DD
= 3 V, 125 μA typ @ AV
DD
= 5 V,
unbuffered mode, external reference
130 μA typ @ AV
DD
= 3 V, 165 μA typ @ AV
DD
= 5 V,
buffered mode, gain = 1 or 2, external reference
300 μA typ @ AV
DD
= 3 V, 350 μA typ @ AV
DD
= 5 V,
gain = 4 to 128, external reference
400 μA typ @ AV
DD
= 3 V, 450 μA typ @ AV
DD
= 5 V,
gain = 4 to 128, internal reference
I
DD
(Power-Down Mode)
1
1
Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal
mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AV
DD
− 16 V typically. When this voltage is exceeded,
the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the
absolute voltage on the analog input pins needs to be below AV
DD
− 1.6 V.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.
4
Recalibration at any temperature removes these errors.
5
Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV
DD
= 4 V, gain = 1, T
A
= 25°C).
6
FS[3:0] are the four bits used in the mode register to select the output word rate.
7
Digital inputs equal to DV
DD
or GND with excitation currents and bias voltage generator disabled.
