REV. B
781/329-4700
781/461-3113
AD783–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
SAMPLING CHARACTERISTICS
Acquisition Time
5 V Step to 0.01%
5 V Step to 0.1%
Small Signal Bandwidth
Full Power Bandwidth
HOLD CHARACTERISTICS
Effective Aperture Delay (+25°C)
Aperture Jitter (+25°C)
Hold Settling (to 1 mV, +25°C)
Droop Rate
Feedthrough (+25°C)
(V
IN
=
±
2.5 V, 500 kHz)
ACCURACY CHARACTERISTICS
1
Hold Mode Offset
Hold Mode Offset Drift
Sample Mode Offset
Nonlinearity
Gain Error
OUTPUT CHARACTERISTICS
Output Drive Current
Output Resistance, DC
Total Output Noise (DC to 5 MHz)
Sampled DC Uncertainty
Hold Mode Noise (DC to 5 MHz)
Short Circuit Current
Source
Sink
INPUT CHARACTERISTICS
Input Voltage Range
Bias Current
Input Impedance
Input Capacitance
DIGITAL CHARACTERISTICS
Input Voltage Low
Input Voltage High
Input Current High (V
IN
= 5 V)
POWER SUPPLY CHARACTERISTICS
Operating Voltage Range
Supply Current
+PSRR (+5 V
±
5%)
–PSRR (–5 V
±
5%)
Power Consumption
TEMPERATURE RANGE
Specified Performance (J)
Specified Performance
NOTES
1
Specified and tested over an input range of
±
2.5 V.
Specifications subject to change without notice.
(T
MIN
to T
MAX
with V
CC
= +5 V
5%, V
EE
= –5 V
Min
5%, C
L
= pF, unless otherwise noted)
AD783J
Typ
Max
Units
250
200
15
2
–30
15
20
150
0.02
–80
–5
0
10
50
±
0.005
±
0.03
375
350
ns
ns
MHz
MHz
ns
ps
ns
µV/µs
dB
30
50
200
1
+5
200
±
0.1
+5
0.6
mV
µV/°C
mV
% FS
% FS
mA
Ω
µV
rms
µV
rms
µV
rms
mA
mA
V
nA
MΩ
pF
V
V
µA
V
mA
dB
dB
mW
°C
–5
0.3
150
85
125
20
13
–2.5
100
10
2
+2.5
250
0.8
2.0
2
±
4.75
45
45
±
5
9.5
65
65
95
10
±
5.25
17
175
+70
0
–2–
REV. B
AD783
HOLD MODE AC SPECIFICATIONS
(T
Parameter
TOTAL HARMONIC DISTORTION
f
IN
= 100 kHz
f
IN
= 500 kHz
SIGNAL-TO-NOISE AND DISTORTION
f
IN
= 100 kHz
f
IN
= 500 kHz
INTERMODULATION DISTORTION
(F1 = 99 kHz, F2 = 100 kHz)
Second Order Products
Third Order Products
NOTES
1
f
IN
amplitude = 0 dB and f
SAMPLE
= 300 kHz unless otherwise indicated.
Specifications subject to change without notice.
MIN
to T
MAX
with V
CC
= +5 V
5%, V
EE
= –5 V
AD783J
Typ
–85
–72
77
70
5%, C
L
= 50 pF, unless otherwise noted)
Max
–80
Units
dB
dB
dB
dB
Min
–80
–85
dB
dB
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Spec
V
CC
V
EE
Analog Input
Digital Input
Output Short Circuit to
Ground, V
CC
,
or V
EE
Maximum Junction
Temperature
Storage
Lead Temperature
(10 sec max)
With
Respect to
COM
COM
COM
COM
Min
–0.5
–6.5
–6.5
–0.5
Max
+6.5
+0.5
+6.5
+6.5
Units
V
V
V
V
V
CC
IN
COMMON
NC
1
2
3
4
NC = NO CONNECT
8
OUT
S/H
NC
V
EE
AD783
TOP VIEW
(Not to Scale)
7
6
5
Indefinite
+175
°C
+150
°C
+300
°C
–65
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD783 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD783–Typical Characteristics
10.0
V+
60
V–
1.0
DROOP RATE –
µV/µs
PSRR – dB
50
0.1
40
0.01
30
0
1
10
100
1k
10k
100k
1M
FREQUENCY – Hz
0.001
0
25
50
75
100
TEMPERATURE –
°
C
125
150
Power Supply Rejection Ratio vs. Frequency
Droop Rate vs. Temperature, V
IN
= 0 V
200
150
100
BIAS CURRENT – nA
50
0
–50
–100
–150
ACQUISITION TIME – ns
300
250
200
0
–200
–2.5
0
INPUT VOLTAGE – V
0
+2.5
1
2
3
INPUT STEP – V
4
5
Bias Current vs. Input Voltage
Acquisition Time (to 0.01%) vs. Input Step Size
–4–
REV. B
AD783
DEFINITIONS OF SPECIFICATIONS
Acquisition Time—The
length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth—The
frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth—The
frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 5 V p-p sine wave.
Effective Aperture Delay—The
difference between the switch
delay and the analog delay of the SHA channel. A negative
number indicates that the analog portion of the overall delay is
greater than the switch portion. This effective delay represents
the point in time, relative to the hold command, that the input
signal will be sampled.
Aperture Jitter—The
variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time—The
time required for the output to
settle to within a specified level of accuracy of its final held value
after the hold command has been given.
Droop Rate—The
drift in output voltage while in the hold
mode.
Feedthrough—The
attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset—The
difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Sample Mode Offset—The
difference between the input and
output signals when the SHA is in the sample mode.
Nonlinearity—The
deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –2.5 V and +2.5 V.
Gain Error—Deviation
from a gain of +1 on the transfer
function of input vs. held output.
Power Supply Rejection Ratio—A
measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled DC Uncertainty—The
internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise—The
rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise—The
total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current—The
maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D
is
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels.
Total Harmonic Distortion (THD)—THD
is the ratio of the
rms sum of the first six harmonic components to the rms value
of the measured input signal and is expressed in decibels.
Intermodulation Distortion (IMD)—With
inputs consisting
of sine waves at two frequencies, fa and fb, any device with
nonlinearities will create distortion products, of order (m+n), at
sum and difference frequency of mfa± nfb, where m, n = 0, 1, 2,
3. . . . Intermodulation terms are those for which m or n is not
equal to zero. For example, the second order terms are (fa+fb)
and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb),
(fa+2fb) and (fa–2fb). The IMD products are expressed as the
decibel ratio of the rms sum of the measured input signals to the
rms sum of the distortion terms. The two signals are of equal
amplitude, and peak value of their sums is –0.5 dB from full
scale. The IMD products are normalized to a 0 dB input signal.
FUNCTIONAL DESCRIPTION
The AD783 is a complete, high speed sample-and-hold
amplifier that provides high speed sampling to 12-bit accuracy
in 250 ns.
The AD783 is completely self-contained, including an on-chip
hold capacitor, and requires no external components or adjust-
ments to perform the sampling function. Both input and output
are treated as a single-ended signal, referred to common.
The AD783 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. Below is a block diagram of the
AD783.
1
2
X1
V
CC
IN
COMMON
NC
8
7
6
OUT
S/H
NC
V
EE
3
4
AD783
NC = NO CONNECT
5
Functional Block Diagram
REV. B
–5–
