The AD7874 is a four-channel simultaneous sampling, 12-bit
data acquisition system. The part contains a high speed 12-bit
ADC, on-chip reference, on-chip clock and four track/hold am-
plifiers. This latter feature allows the four input channels to be
sampled simultaneously, thus preserving the relative phase
information of the four input channels, which is not possible if
all four channels share a single track/hold amplifier. This makes
the AD7874 ideal for applications such as phased-array sonar
and ac motor controllers where the relative phase information is
important.
The aperture delay of the four track/hold amplifiers is small and
specified with minimum and maximum limits. This allows sev-
eral AD7874s to sample multiple input channels simultaneously
without incurring phase errors between signals connected to
several devices. A reference output/reference input facility also
allows several AD7874s to be driven from the same reference
source.
In addition to the traditional dc accuracy specifications such as
linearity, full-scale and offset errors, the AD7874 is also fully
specified for dynamic performance parameters including distor-
tion and signal-to-noise ratio.
The AD7874 is fabricated in Analog Devices’ Linear Compat-
ible CMOS (LC
2
MOS) process, a mixed technology process
that combines precision bipolar circuits with low-power CMOS
logic. The part is available in a 28-pin, 0.6" wide, plastic or her-
metic dual-in-line package (DIP), in a 28-terminal leadless ce-
ramic chip carrier (LCCC) and in a 28-pin SOIC.
3V
REFERENCE
AGND DGND
V
SS
REF OUT
PRODUCT HIGHLIGHTS
1. Simultaneous Sampling of Four Input Channels.
Four input channels, each with its own track/hold amplifier,
allow simultaneous sampling of input signals. Track/hold ac-
quisition time is 2
µs,
and the conversion time per channel is
8
µs,
allowing 29 kHz sample rate for all four channels.
2. Tight Aperture Delay Matching.
The aperture delay for each channel is small and the aperture
delay matching between the four channels is less than 4 ns.
Additionally, the aperture delay specification has upper and
lower limits allowing multiple AD7874s to sample more than
four channels.
3. Fast Microprocessor Interface.
The high speed digital interface of the AD7874 allows direct
connection to all modern 16-bit microprocessors and digital
signal processors.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7874–SPECIFICATIONS
Parameter
SAMPLE-AND-HOLD
Acquisition Time
2
to 0.01%
Droop Rate
2, 3
–3 dB Small Signal Bandwidth
3
Aperture Delay
2
Aperture Jitter
2, 3
Aperture Delay Matching
2
SAMPLE-AND-HOLD AND ADC
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion
2nd Order Terms
3rd Order Terms
Channel-to-Channel Isolation
2
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Positive Full-Scale Error
4
Negative Full-Scale Error
4
Full-Scale Error Match
Bipolar Zero Error
Bipolar Zero Error Match
ANALOG INPUTS
Input Voltage Range
Input Current
REFERENCE OUTPUTS
REF OUT
REF OUT Error @ +25°C
T
MIN
to T
MAX
REF OUT Temperature Coefficient
Reference Load Change
REFERENCE INPUT
Input Voltage Range
Input Current
Input Capacitance
3
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB0–DB11
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
Power Dissipation
2
1
500
0
40
200
4
2
1
500
0
40
200
4
(V
DD
= +5 V, V
SS
= –5 V, AGND = DGND = 0 V, REF IN = +3 V, f
CLK
= 2.5 MHz
external. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Test Conditions/Comments
A Version B Version S Version Units
2
2
500
0
40
200
4
µs
max
mV/ms max
kHz typ
ns min
ns max
ps typ
ns max
V
IN
= 500 mV p-p
70
–78
–78
–80
–80
–80
12
±
1
±
1
±
5
±
5
5
±
5
4
±
10
±
600
3
±
0.33
±
1
±
35
±
1
71
–80
–80
–80
–80
–80
12
±
1/2
±
1
±
5
±
5
5
±
5
4
±
10
±
600
3
±
0.33
±
1
±
35
±
1
70
–78
–78
–80
–80
–80
12
±
1
±
1
±
5
±
5
5
±
5
4
±
10
±
600
3
±
0.33
±
1
±
35
±
2
dB min
dB max
dB max
dB max
dB max
dB max
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Volts
µA
max
V nom
% max
% max
ppm/°C typ
mV max
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 29 kHz
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 29 kHz
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 29 kHz
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 29 kHz
No Missing Codes Guaranteed
Any Channel
Any Channel
Between Channels
Any Channel
Between Channels
Reference Load Current Change (0–500
µA)
Reference Load Should Not Be Changed During Conversion
2.85/3.15
±
1
10
2.4
0.8
±
10
10
4.0
0.4
±
10
10
2.85/3.15
±
1
10
2.4
0.8
±
10
10
4.0
0.4
2.85/3.15
±
1
10
2.4
0.8
±
10
10
4.0
0.4
V min/V max 3 V
±
5%
µA
max
pF max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
V
DD
= 5 V
±
5%; I
SOURCE
= 40
µA
V
DD
= 5 V
±
5%; I
SINK
= 1–6 mA
V
IN
= 0 V to V
DD
±
10
±
10
10
10
2s COMPLEMENT
+5
–5
18
12
150
+5
–5
18
12
150
+5
–5
18
12
150
V nom
V nom
mA max
mA max
mW max
±
5% for Specified Performance
±
5% for Specified Performance
CS
=
RD
=
CONVST
= +5 V; Typically 12 mA
CS
=
RD
=
CONVST
= +5 V; Typically 8 mA
CS
=
RD
=
CONVST
= +5 V; Typically 100 mW
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2
See Terminology.
3
Sample tested @ +25°C to ensure compliance.
4
Measured with respect to the REF IN voltage and includes bipolar offset error.
5
For capacitive loads greater than 50 pF a series resistor is required.
Specifications subject to change without notice.
–2–
REV. C
AD7874
TIMING CHARACTERISTICS
Parameter
t
1
t
2
t
3
t
4
t
5
t
6 2
t
7 3
t
8
t
CONV
A, B Versions
50
0
60
0
60
57
5
45
130
31
32.5
31
35
10
1
(V
DD
= +5 V
5%, V
SS
= –5 V
otherwise noted.)
S Version
50
0
70
0
60
70
5
50
150
31
32.5
31
35
10
5%, AGND = DGND = O V, t
CLK
= 2.5 MHz external unless
Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
µs
min
µs
max
µs
min
µs
max
µs
max
Conditions/Comments
CONVST
Pulse Width
CS
to
RD
Setup Time
RD
Pulse Width
CS
to
RD
Hold Time
RD
to
INT
Delay
Data Access Time after
RD
Bus Relinquish Time after
RD
Delay Time between Reads
CONVST
to
INT,
External Clock
CONVST
to
INT,
External Clock
CONVST
to
INT,
Internal Clock
CONVST
to
INT,
Internal Clock
Minimum Input Clock Period
t
CLK
NOTES
1
Timing Specifications in
bold print
are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t
6
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
IN
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
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