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LC MOS Complete 12-Bit
100 kHz Sampling ADC with DSP Interface
AD7878
FUNCTIONAL BLOCK DIAGRAM
2
FEATURES
Complete ADC with DSP Interface, Comprising:
Track/Hold Amplifier with 2 s Acquisition Time
7 s A/D Converter
3 V Zener Reference
8-Word FIFO and Interface Logic
72 dB SNR at 10 kHz Input Frequency
Interfaces to High Speed DSP Processors, e.g.,
ADSP-2100, TMS32010, TMS32020
41 ns max Data Access Time
Low Power, 60 mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
GENERAL DESCRIPTION
The AD7878 is a fast, complete, 12-bit A/D converter with a
versatile DSP interface consisting of an 8-word, first-in, first-out
(FIFO) memory and associated control logic.
The FIFO memory allows up to eight samples to be digitized
before the microprocessor is required to service the A/D con-
verter. The eight words can then be read out of the FIFO at
maximum microprocessor speed. A fast data access time of
41 ns allows direct interfacing to DSP processors and high
speed 16-bit microprocessors.
An on-chip status/control register allows the user to program the
effective length of the FIFO and contains the FIFO out of
range, FIFO empty and FIFO word count information.
The analog input of the AD7878 has a bipolar range of
±
3 V.
The AD7878 can convert full power signals up to 50 kHz and is
fully specified for dynamic parameters such as signal-to-noise
ratio and harmonic distortion.
The AD7878 is fabricated in Linear Compatible CMOS
(LC
2
MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
The part is available in four package styles, 28-pin plastic and
hermetic dual-in-line package (DIP), leadless ceramic chip
carrier (LCCC) or plastic leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTS
1. Complete A/D Function with DSP Interface
The AD7878 provides the complete function for digitizing
ac signals to 12-bit accuracy. The part features an on-chip
track/hold, on-chip reference and 12-bit A/D converter. The
additional feature of an 8-word FIFO reduces the high soft-
ware overheads associated with servicing interrupts in DSP
processors.
2. Dynamic Specifications for DSP Users
The AD7878 is fully specified and tested for ac parameters,
including signal-to-noise ratio, harmonic distortion and
intermodulation distortion. Key digital timing parameters
are also tested and specified over the full operating tempera-
ture range.
3. Fast Microprocessor Interface
Data access time of 41 ns is the fastest ever achieved in a
monolithic A/D converter, and makes the AD7878 compat-
ible with all modern 16-bit microprocessors and digital
signal processors.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD7878–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio (SNR)
3
@ 25°C
T
MIN
to T
MAX
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Track/Hold Acquisition Time
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes are Guaranteed
Relative Accuracy
Differential Nonlinearity
Bipolar Zero Error
Positive Full-Scale Error
4
Negative Full-Scale Error
4
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT
5
REF OUT
REF OUT Error @ 25°C
T
MIN
to T
MAX
Reference Load Sensitivity
(∆REF OUT/∆I)
70
70
–80
–80
(V
DD
= +5 V 5%, V
CC
= +5 V 5%, V
SS
= –5 V 5%, AGND = DGND =
0 V, f
CLK
= 8 MHz. All Specifications T
MIN
to T
MAX
, unless otherwise noted.)
Units
dB min
dB min
dB max
dB max
Test Conditions/Comments
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 100 kHz
Typically 71.5 dB for 0 < V
IN
< 50 kHz
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 100 kHz
Typically –86 dB for 0 < V
IN
< 50 kHz
V
IN
= 10 kHz, f
SAMPLE
= 100 kHz
Typically –86 dB for 0 < V
IN
< 50 kHz
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
See Throughput Rate Section
J, A
K, L, B S
1
Versions Versions Version
72
71
–80
–80
70
70
–78
–78
–80
–80
2
12
12
±
1/2
±
1/2
±
6
±
6
±
6
±
3
±
550
3
±
10
±
15
±
1
–80
–80
2
12
12
±
1/4
±
1/2
±
6
±
6
±
6
±
3
±
550
3
±
10
±
15
±
1
–78
–78
2
12
12
±
1/2
±
1/2
±
6
±
6
±
6
±
3
±
550
3
±
10
±
15
±
1
dB max
dB max
µs
max
Bits
Bits
LSB typ
LSB typ
LSB max
LSB max
LSB max
Volts
µA
max
V nom
mV max
mV max
mV max
Reference Load Current Change (0
µA–500 µA).
Reference Load Should Not Be Changed
During Conversion
V
CC
= +5 V
±
5%
V
CC
= +5 V
±
5%
V
IN
= 0 to V
CC
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN6
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB11–DB0
Floating State Leakage Current
Floating State Output Capacitance
6
CONVERSION TIME
+2.4
+0.8
±
10
10
+2.7
+0.4
±
10
15
7/7.125
7/9.250
+2.4
+0.8
±
10
10
+2.7
+0.4
±
10
15
7/7.125
7/9.250
+2.4
+0.8
±
10
10
+2.7
+0.4
±
10
15
7/7.125
7/9.250
V min
V max
µA
max
pF max
V min
V max
±
10
15
µs
min/µs max
µs
min/µs max
I
SOURCE
40
µA
I
SINK
= 1.6 mA
µA
max
pF max
Assuming No External Read/Write Operations
Assuming 17 External Read/Write Operations
See Internal Comparator Timing Section
±
5% for Specified Performance
±
5% for Specified Performance
±
5% for Specified Performance
CS
=
DMWR
=
DMRD
= 5 V
CS
=
DMWR
=
DMRD
= 5 V
CS
=
DMWR
=
DMRD
= 5 V
Typically 60 mW
POWER REQUIREMENTS
V
DD
V
CC
V
SS
I
DD
I
CC
I
SS
Power Dissipation
+5
+5
–5
13
100
6
95.5
+5
+5
–5
13
100
6
95.5
+5
+5
–5
13
100
6
95.5
V nom
V nom
V nom
mA max
µA
max
mA max
mW max
NOTES
1
Temperature range as follows: J, K, L versions: 0°C to +70°C; A, B versions: –25°C to +85°C; S version: –55°C to +125°C.
2
V
IN
=
±
3 V. See Dynamic Specifications section.
3
SNR calculation includes distortion and noise components.
4
Measured with respect to the Internal Reference.
5
For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
6
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. A
AD7878
TIMING CHARACTERISTICS
1
(V
Limit at T
MIN
, T
MAX
Parameter (L Grade)
t
l
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
92
t
103
t
11
t
12
t
13
t
142
t
RESET
65
65
2 CLK IN Cycles
0
0
45
50
16
0
41
5
45
42
50
20
10
41
2 CLK IN Cycles
DD
=5V
5%, V
CC
= 5 V
5%, V
SS
= –5 V
Units
ns max
ns max
min
ns min
ns min
ns min
µs
max
ns min
ns min
ns min
ns min
ns max
ns min
µs
max
ns min
ns min
ns min
min
5%)
Conditions/Comments
CLK IN to
BUSY
Low Propagation Delay
CLK IN to
BUSY
High Propagation Delay
CONVST
Pulse Width
CS
to
DMRD/REGISTER
ENABLE Setup Time
CS
to
DMRD/
REGISTER ENABLE Hold Time
DMRD
Pulse Width
ADD0 to
DMRD/REGISTER
ENABLE Setup Time
ADD0 to
DMRD/REGISTER
ENABLE Hold Time
Data Access Time after
DMRD
Bus Relinquish Time
REGISTER ENABLE Pulse Width
Data Valid to REGISTER ENABLE Setup Time
Data Hold Time after REGISTER ENABLE
Data Access Time after BUSY
RESET Pulse Width
Limit at T
MIN
, T
MAX
(J, K, A, B Grades)
65
65
2 CLK IN Cycles
0
0
60
50
16
0
57
5
45
42
50
20
10
57
2 CLK IN Cycles
Limit at T
MIN
, T
MAX
(S Grade)
75
75
2 CLK IN Cycles
0
0
60
50
16
0
57
5
45
55
50
30
10
57
2 CLK IN Cycles
NOTES
1
Timing Specifications in
bold
print are 100% production tested. All other times are sample tested at +25
°C
to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
9
and t
14
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
10
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise stated)
a. High-Z to V
OH
b. High-Z to V
OL
Figure 1. Load Circuits for Access Time
a. V
OH
to High-Z
b. V
OL
to High-Z
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
V
DD
to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
V
IN
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
DD
Digital Inputs to DGND
CLK IN,
DMWR, DMRD, RESET,
CS, CONVST,
ADD0 . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Digital Outputs to DGND
ALFL, BUSY
. . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Data Pins
DB11–DB0 . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Operating Temperature Range
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
Figure 2. Load Circuits for Output Float Delay
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7878 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD7878
PIN FUNCTION DESCRIPTION
Pin
Number
11
Pin
Mnemonic
ADD0
Function
Address Input. This control input determines whether the word placed on the output data bus during a read operation is a data
word from the FIFO RAM or the contents of the status/control register. A logic low accesses the data word from Location 0 of
the FIFO while a logic high selects the contents of the register (see Status/Control Register section).
Chip Select. Active low logic input. The device is selected when this input is active.
Dam Memory Write. Active low logic input.
DMWR
is used in conjunction with
CS
low and ADD0 high to write data to the
status/control register. Corresponds to
DMWR
(ADSP-2100), R/W (MC68000, TMS32020),
WE
(TMS32010).
Data Memory READ. Active low logic input.
DMRD
is used in conjunction with
CS
low to enable the three-state output buffers.
Corresponds directly to
DMRD
(ADSP-2100),
DEN
(TMS32010).
Active Low Logic Output. This output goes low when the ADC receives a
CONVST
pulse and remains low until the track/hold
has gone into its hold mode. The three-state drivers of the AD7878 can be disabled while the
BUSY
signal is low (see Extended
READ/WRITE section). This is achieved by writing a logic 0 to DB5 (DISO) of the status/control register. Writing a logic 1 to
DB5 of the status/control register allows data to be accessed from the AD7878 while BUSY is low.
FIFO Almost Full. A logic low indicates that the word count (i.e., number of conversion results) in the FIFO memory has
reached the programmed word count in the status/control register.
ALFL
is updated at the end of each conversion. The
ALFL
output is reset to a logic high when a word is read from the FIFO memory and the word count is less than the preprogrammed
word count. It can also be set high by writing a logic 1 to DB7 (ENAF) of the status/control register.
Digital Ground. Ground reference for digital circuitry.
Digital supply voltage, +5 V
±
5%. Positive supply voltage for digital circuitry.
Data Bit 11 (MSB). Three-state TTL output. Coding for the data words in FIFO RAM is twos complement.
Data Bit 10 to Data Bit 5. Three-state TTL input/outputs.
Data Bit 4 to Data Bit 1. Three-state TTL outputs.
Data Bit 0 (LSB). Three-state TTL output.
Analog positive supply voltage, +5 V
±
5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
Voltage Reference Output. The internal 3 V analog reference is provided at this pin. The external load capability of the reference
is 500
µA.
Analog Input. Analog input range is
±
3 V.
Analog negative supply voltage, –5 V
±
5%.
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.
The
CONVST
input is asynchronous to CLK IN and independent of
CS, DMWR
and
DMRD.
Reset. Active low logic input. A logic low sets the words in FIFO memory to 1000 0000 0000 and resets the
ALFL
output and
status/control register.
Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark-space ratio of this clock can
vary from 35/65 to 65/35.
12
13
14
15
CS
DMWR
DMRD
BUSY
16
ALFL
17
18
19
10–15
16–19
20
21
22
23
24
25
26
27
28
DGND
V
CC
DB11
DB10–DB5
DB4–DB1
DB0
V
DD
AGND
REF OUT
V
IN
V
SS
CONVST
RESET
CLK IN
PIN CONFIGURATIONS
DIP
PLCC
LCCC
–4–
REV. A
