One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
= +5 V 5%, V
SS
= –5 V
= +3 V; AGND = DGND = GND = 0 V; f
SAMPLE
= 166 kHz. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
DD
AD7884/AD7885/AD7885A–SPECIFICATIONS
(V
A
B
Version
1, 2, 3
Versions
1, 2, 3
16
16
±
0.03
±
2
±
0.05
±
8
±
0.03
±
2
120
84
82
–88
–84
–88
–84
–84
5.3
2.5
166
±
5
±
3
±
4
±
5
2.4
0.8
±
10
10
4.0
0.4
10
15
+5
–5
35
30
86
86
325
16
16
±
0.0075
±
0.03
±
0.05
±
2
±
0.05
±
0.15
±
8
±
0.03
±
0.05
±
2
120
84
82
–88
–84
–88
–84
–84
5.3
2.5
166
±
5
±
3
±
4
±
5
2.4
0.8
±
10
10
4.0
0.4
10
15
+5
–5
35
30
86
86
325
Units
Bits
Bits
% FSR max
% FSR typ
% FSR max
ppm FSR/°C typ
% FSR typ
% FSR max
ppm FSR/°C typ
% FSR typ
% FSR max
ppm FSR/°C typ
µV
rms typ
dB min
dB typ
dB max
dB typ
dB max
dB typ
dB typ
µs
max
µs
max
kSPS max
Volts
Volts
mA max
mA max
V min
V max
µA
max
pF max
V min
V max
µA
max
pF max
V nom
V nom
mA max
mA max
dB typ
dB typ
mW max
5%, V
REF
+S
Parameter
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity
Positive Gain Error
Positive Gain Error
Gain TC
4
Bipolar Zero Error
Bipolar Zero Error
Bipolar Zero TC
4
Negative Gain Error
Negative Gain Error
Offset TC
4
Noise
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
2nd Order Terms
3rd Order Terms
CONVERSION TIME
Conversion Time
Acquisition Time
Throughput Rate
ANALOG INPUT
Voltage Range
Input Current
REFERENCE INPUT
Reference Input Current
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB15–DB0
Floating-State Leakage Current
Floating-State Output Capacitance
4
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
Power Supply Rejection Ratio
∆Gain/∆V
DD
∆Gain/∆V
SS
Power Dissipation
Test Conditions/Comments
Typically 0.003% FSR
AD7885AN/BN: 0.1% typ
AD7885BN: 0.2% max
AD7885AN/BN: 0.1% typ
AD7885BN: 0.2% max
78
µV
rms typical in
±
3 V Input Range
Input Signal:
±
5 V, 1 kHz Sine Wave, Typically 86 dB
Input Signal:
±
5 V, 12 kHz Sine Wave
Input Signal:
±
5 V, 1 kHz Sine Wave
Input Signal:
±
5 V, 12 kHz Sine Wave
Input Signal:
±
5 V, 1 kHz Sine Wave
f
A
= 11.5 kHz, f
B
= 12 kHz, f
SAMPLE
= 166 kHz
f
A
= 11.5 kHz, f
B
= 12 kHz, f
SAMPLE
= 166 kHz
There is an overlap between conversion and acquisition.
V
REF
+ S = +3 V
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
Input Level = 0 V to V
DD
I
SOURCE
= 40
µA
I
SINK
= 1.6 mA
±
5% for Specified Performance
±
5% for Specified Performance
Typically 25 mA
Typically 25 mA
Typically 250 mW
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C.
2
V
IN
=
±
5 V.
3
The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP.
4
Sample tested to ensure compliance.
Specifications subject to change without notice.
–2–
REV. C
AD7884/AD7885
TIMING CHARACTERISTICS
1, 2
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6 2
t
7 3
t
8
t
9
t
10
t
11
t
12
t
13
t
14
Limit at +25 C
(All Versions)
50
100
0
60
0
57
5
50
40
10
25
60
60
55
55
50
100
0
60
0
57
5
50
40
80
25
60
60
70
70
DD
= +5 V
5%, V
SS
= –5 V
Units
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)
Conditions/Comments
CONVST
Pulse Width
CONVST
to
BUSY
Low Delay
CS
to
RD
Setup Time
RD
Pulse Width
CS
to
RD
Hold Time
Data Access Time after
RD
Bus Relinquish Time after
RD
New Data Valid before Rising Edge of
BUSY
HBEN to
RD
Setup Time
HBEN to
RD
Hold Time
HBEN Low Pulse Duration
HBEN High Pulse Duration
Propagation Delay from HBEN Falling to Data Valid
Propagation Delay from HBEN Rising to Data Valid
Limit at T
MIN
, T
MAX
(A, B Versions)
NOTES
1
Timing specifications in
bold
print are 100% production tested. All other times are sample tested at +5
°C
to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
6
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap-
olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
7
, quoted in the Timing Characteristics is the true
bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
ORDERING GUIDE
Model
1
Linearity
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Error
(% FSR)
±
0.0075
±
0.0075
±
0.0075
±
0.0075
SNR
(dB)
84
84
84
84
84
84
84
84
Package
Option
2
N-40A
N-40A
P-44A
P-44A
N-28A
N-28A
P-44A
P-44A
1.6mA
I
OL
AD7884AN
AD7884BN
AD7884AP
AD7884BP
AD7885AN
AD7885BN
AD7885AAP
AD7885ABP
TO OUTPUT PIN
+2.1V
C
L
100pF
200µA
I
OH
NOTES
1
Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic
DIP (N) packages.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).
Figure 1. Load Circuit for Access Time and Bus Relinquish
AUXR DATA 08EH ;Auxiliary register P1M1 DATA 091H ;P1M1.N,P1M0.N =00--- Standard, 01--- push-pull P1M0 DATA 092H ; =10--- pure input, 11--- open drain...[详细]
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