Low Power, 350 MHz
Voltage Feedback Amplifiers
AD8038/AD8039
FEATURES
Low power: 1 mA supply current/amp
High speed
350 MHz, −3 dB bandwidth (G = +1)
425 V/μs slew rate
Low cost
Low noise
8 nV/√Hz @ 100 kHz
600 fA/√Hz @ 100 kHz
Low input bias current: 750 nA maximum
Low distortion
−90 dB SFDR @ 1 MHz
−65 dB SFDR @ 5 MHz
Wide supply range: 3 V to 12 V
Small packaging: 8-lead SOT-23, 5-lead SC70, and 8-lead SOIC
FUNCTIONAL BLOCK DIAGRAM
NC
1
–IN
2
+IN
3
–V
S 4
AD8038
8
7
6
5
DISABLE
+V
S
V
OUT
02951-001
NC
NC = NO CONNECT
Figure 1. 8-lead SOIC (R)
V
OUT 1
–V
S 2
+IN
3
4
AD8038
5
+V
S
–IN
Figure 2. 5-Lead SC70 (KS)
AD8039
V
OUT1 1
–IN1
2
+IN1
3
–V
S 4
8
7
6
5
APPLICATIONS
Battery-powered instrumentation
Filters
A/D drivers
Level shifting
Buffering
Photo multipliers
+V
S
V
OUT2
–IN2
+IN2
02951-003
NC = NO CONNECT
Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ)
GENERAL DESCRIPTION
The AD8038 (single) and AD8039 (dual) amplifiers are high speed
(350 MHz) voltage feedback amplifiers with an exceptionally low
quiescent current of 1.0 mA/amplifier typical (1.5 mA maximum).
The AD8038 single amplifier in the 8-lead SOIC package has a
disable feature. Despite being low power and low cost, the amplifier
provides excellent overall performance. Additionally, it offers a
high slew rate of 425 V/μs and a low input offset voltage of 3 mV
maximum.
The Analog Devices, Inc., proprietary XFCB process allows low
noise operation (8 nV/√Hz and 600 fA/√Hz) at extremely low
quiescent currents. Given a wide supply voltage range (3 V to 12 V),
wide bandwidth, and small packaging, the AD8038 and AD8039
amplifiers are designed to work in a variety of applications
where power and space are at a premium.
The AD8038 and AD8039 amplifiers have a wide input common-
mode range of 1 V from either rail and swing to within 1 V of each
rail on the output. These amplifiers are optimized for driving
capacitive loads up to 15 pF. If driving larger capacitive loads, a small
series resistor is needed to avoid excessive peaking or overshoot.
The AD8039 amplifier is available in a 8-lead SOT-23 package,
and the single AD8038 is available in both an 8-lead SOIC and a
5-lead SC70 package. These amplifiers are rated to work over
the industrial temperature range of −40°C to +85°C.
24
21
18
15
GAIN (dB)
12
9
6
3
0
–3
1
10
FREQUENCY (MHz)
100
1000
02951-004
G = +10
G = +5
G = +2
G = +1
–6
0.1
Figure 4. Small Signal Frequency Response for Various Gains,
V
OUT
= 500 mV p-p, V
S
= ±5 V
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
02951-002
AD8038/AD8039
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Maximum Power Dissipation ..................................................... 5
Output Short Circuit .................................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Layout, Grounding, and Bypassing Considerations .................. 13
Disable ......................................................................................... 13
Power Supply Bypassing ............................................................ 13
Grounding ................................................................................... 13
Input Capacitance ...................................................................... 13
Output Capacitance ................................................................... 13
Input-to-Output Coupling ........................................................ 13
Applications Information .............................................................. 14
Low Power ADC Driver ............................................................ 14
Low Power Active Video Filter ................................................. 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
8/09—Rev. F to Rev. G
Changes to Applications Section and General Description
Section ................................................................................................ 1
Changes to Disable Section and Grounding Section ................. 13
Changes to Low Power ADC Driver Section and Low Power
Active Video Filter Section ............................................................ 14
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
8/04—Rev. E to Rev. F
Changes to Figure 4 ........................................................................ 10
8/03—Rev. D to Rev. E
Change to TPC 34............................................................................. 8
7/03—Rev. C to Rev. D
Changes to Ordering Guide ............................................................ 4
Updated TPC 35 Caption ................................................................ 8
6/03—Rev. B to Rev. C
Updated Connection Diagrams ...................................................... 1
Updated Ordering Guide ................................................................. 4
Updated Outline Dimensions ....................................................... 11
5/02—Rev. A to Rev. B
Add Part Number AD8038 ............................................... Universal
Changes to Product Title ..................................................................1
Changes to Features ..........................................................................1
Changes to Product Description .....................................................1
Changes to Connection Diagram ....................................................1
Update to Specifications ...................................................................2
Update to Maximum Power Dissipation ........................................4
Update to Output Short Circuit.......................................................4
Update to Ordering Guide ...............................................................4
Change to Figure 2 ............................................................................4
Change to TPC 2 ...............................................................................5
Change to TPC 18 .............................................................................6
Change to TPC 27 .............................................................................7
Change to TPC 29 .............................................................................8
Change to TPC 30 .............................................................................8
Change to TPC 31 .............................................................................8
Added TPC 36....................................................................................8
Added TPC 37....................................................................................9
Edits to Low Power Active Video Filter....................................... 10
Change to Figure 4 ......................................................................... 10
4/02—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Update Specifications ................................................................... 2, 3
Edits to TPC 19 ..................................................................................7
Rev. G | Page 2 of 16
AD8038/AD8039
SPECIFICATIONS
T
A
= 25°C, V
S
= ±5 V, R
L
= 2 kΩ, Gain = +1, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Conditions
G = +1, V
O
= 0.5 V p-p
G = +2, V
O
= 0.5 V p-p
G = +1, V
O
= 2 V p-p
G = +2, V
O
= 0.2 V p-p
G = +1, V
O
= 2 V step, R
L
= 2 kΩ
G = +2, 1 V overdrive
G = +2, V
O
= 2 V step
Min
300
Typ
350
175
100
45
425
50
18
Max
Unit
MHz
MHz
MHz
MHz
V/μs
ns
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Overdrive Recovery Time
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
SFDR
Second Harmonic
Third Harmonic
Second Harmonic
Third Harmonic
Crosstalk, Output-to-Output (AD8039)
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
DC Output Voltage Swing
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
POWER-DOWN DISABLE
1
Turn-On Time
Turn-Off Time
Disable Voltage—Part is Off
Disable Voltage—Part is On
Disabled Quiescent Current
Disabled In/Out Isolation
1
400
f
C
= 1 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f
C
= 1 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f = 5 MHz, G = +2
f = 100 kHz
f = 100 kHz
−90
−92
−65
−70
−70
8
600
0.5
4.5
400
3
±25
70
10
2
±4
67
±4
20
3.0
12
1.5
3
750
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
mV
μV/°C
nA
nA/°C
nA
dB
MΩ
pF
V
dB
V
pF
V
mA
dB
dB
ns
ns
V
V
mA
dB
V
O
= ±2.5 V
R
L
= 1 kΩ
V
CM
= ±2.5 V
R
L
= 2 kΩ, saturated output
30% overshoot, G = +2
61
−Supply
+Supply
−71
−64
1.0
−77
−70
180
700
+V
S
− 4.5
+V
S
− 2.5
0.2
−60
f = 1 MHz
Only available in AD8038 8-lead SOIC package.
Rev. G | Page 3 of 16
AD8038/AD8039
T
A
= 25°C, V
S
= 5 V, R
L
= 2 kΩ to V
S
/2, Gain = +1, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Conditions
G = +1, V
O
= 0.2 V p-p
G = +2, V
O
= 0.2 V p-p
G = +1, V
O
= 2 V p-p
G = +2, V
O
= 0.2 V p-p
G = +1, V
O
= 2 V step, R
L
= 2 kΩ
G = +2, 1 V overdrive
G = +2, V
O
= 2 V step
Min
275
Typ
300
150
30
45
365
50
18
Max
Unit
MHz
MHz
MHz
MHz
V/μs
ns
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Overdrive Recovery Time
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
SFDR
Second Harmonic
Third Harmonic
Second Harmonic
Third Harmonic
Crosstalk, Output-to-Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
DC Output Voltage Swing
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
POWER-DOWN DISABLE
1
Turn-On Time
Turn-Off Time
Disable Voltage—Part is Off
Disable Voltage—Part is On
Disabled Quiescent Current
Disabled In/Out Isolation
1
340
f
C
= 1 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f
C
= 1 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 2 kΩ
f = 5 MHz, G = +2
f = 100 kHz
f = 100 kHz
−82
−79
−60
−67
−70
8
600
0.8
3
400
3
±30
70
10
2
1.0 − 4.0
65
0.9 − 4.1
20
3
−65
0.9
−71
210
700
+V
S
− 4.5
+V
S
− 2.5
0.2
−60
12
1.5
3
750
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
mV
μV/°C
nA
nA/°C
nA
dB
MΩ
pF
V
dB
V
pF
V
mA
dB
ns
ns
V
V
mA
dB
V
O
= ±2.5 V
R
L
= 1 kΩ
V
CM
= ±1 V
R
L
= 2 kΩ, saturated output
30% overshoot
59
f = 1 MHz
Only available in AD8038 8-lead SOIC package.
Rev. G | Page 4 of 16
AD8038/AD8039
ABSOLUTE MAXIMUM RATINGS
2.0
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
12.6 V
See Figure 5
±V
S
±4 V
−65°C to +125°C
−40°C to +85°C
300°C
MAXIMUM POWER DISSIPATION (W)
1.5
SOIC-8
SOT-23-8
1.0
SC70-5
0.5
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
–25
5
35
65
95
AMBIENT TEMPERATURE (°C)
125
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8038/AD8039
package is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8038/AD8039.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θ
JA
),
ambient temperature (T
A
), and total power dissipated in the
package (P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as
T
J
=
T
A
+ (P
D
×
θ
JA
)
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent power
is the voltage between the supply pins (V
S
) multiplied by the
quiescent current (I
S
). Assuming the load (R
L
) is referenced to
midsupply, then the total drive power is V
S
/2 × I
OUT
, some of which
is dissipated in the package and some in the load (V
OUT
× I
OUT
).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
P
D
=
quiescent power
+ (total
drive power
−
load power)
P
D
= [V
S
×
I
S
] + [(V
S
/2) × (V
OUT
/R
L
)] − [V
OUT
2
/R
L
]
RMS output voltages should be considered. If R
L
is referenced to
V
S−
, as in single-supply operation, then the total drive power is
V
S
× I
OUT
. If the rms signal levels are indeterminate, consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply
P
D
= (V
S
×
I
S
) + (V
S
/4)
2
/R
L
In single-supply operation with R
L
referenced to V
S−
, worst case
is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, throughholes, ground, and power planes reduce
the θ
JA
. Care must be taken to minimize parasitic capacitances at
the input leads of high speed op amps as discussed in the
Layout, Grounding, and Bypassing Considerations section.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23
(160°C/W) packages on a JEDEC standard 4-layer board.
θ
JA
values are approximations.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current
from the AD8038/AD8039 will likely cause a catastrophic failure.
ESD CAUTION
Rev. G | Page 5 of 16
02951-005
0
–55
单片机
