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FEATURES
Single and Dual 2-to-1 Also Available (AD8180 and AD8182)
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
High Speed
> 700 MHz Bandwidth (–3 dB)
> 750 V/ s Slew Rate
Fast Settling Time of 15 ns to 0.1%
Excellent Video Specifications (R
L
> 2 k )
Gain Flatness of 0.1 dB of 75 MHz
0.01% Differential Gain Error, R
L
= 10 k
0.01 Differential Phase Error, R
L
= 10 k
Low Power: 4.4 mA
Low Glitch: < 25 mV
Low All-Hostile Crosstalk of –95 dB @ 5 MHz
High “OFF” Isolation of –115 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple Devices
APPLICATIONS
Pin Compatible with HA4314* and GX4314*
Video Switchers and Routers
Pixel Switching for “Picture-In-Picture”
Switching in LCD and Plasma Displays
700 MHz, 5 mA
4-to-1 Video Multiplexer
AD8184
FUNCTIONAL BLOCK DIAGRAM
IN0 1
GND 2
IN1 3
GND 4
IN2 5
GND 6
IN3 7
+1
+1
DECODER
+1
14 +V
S
13 A0
12 A1
11
ENABLE
10 OUT
9 NC
+1
AD8184
8 –V
S
NC = NO CONNECT
Table I. Truth Table
ENABLE
0
0
0
0
1
A1
0
0
1
1
X
A0
0
1
0
1
X
OUTPUT
IN0
IN1
IN2
IN3
High Z
PRODUCT DESCRIPTION
NORMALIZED OUTPUT – dB
The AD8184 is a high speed 4-to-1 multiplexer. It offers –3 dB
signal bandwidth of 700 MHz along with a slew rate of 750 V/µs.
With 95 dB of crosstalk and 115 dB isolation, it is useful in
many high speed applications. The differential gain and differ-
ential phase error of 0.01% and 0.01°, along with 0.1 dB flatness
of 75 MHz, make AD8184 ideal for professional video multi-
plexing. It offers 10 ns switching time, making it an excellent
choice for pixel switching (picture-in-picture) while consuming
less than 4.5 mA on
±
5 V supply voltage.
The AD8184 offers a high speed disable feature allowing the
output to be put into a high impedance state. This allows mul-
tiple outputs to be connected together for cascading stages while
the “OFF” channels do not load the output bus. It operates on
voltage supplies of
±5
V and is offered in 14-lead PDIP and
SOIC packages.
*All
trademarks are the property of their respective holders.
5
4
3
2
1
0
–1
–2
–3
–4
–5
1M
10M
100M
FREQUENCY – Hz
1G
V
IN
= 50mVrms
R
L
= 5kΩ
Figure 1. Small Signal Frequency Response
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD8184–SPECIFICATIONS
(@ T = +25 C, V =
A
S
5 V, R
L
= 2 k
unless otherwise noted)
AD8184A
Min
Typ
Max
Units
Parameter
SWITCHING CHARACTERISTICS
Channel Switching Time
1
50% Logic to 10% Output Settling
50% Logic to 90% Output Settling
50% Logic to 99.9% Output Settling
ENABLE
to Channel ON Time
2
50% Logic to 90% Output Settling
ENABLE
to Channel OFF Time
2
50% Logic to 90% Output Settling
Channel Switching Transient (Glitch)
3
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Input Current
Logic “0” Input Current
DYNAMIC PERFORMANCE
–3 dB Bandwidth (Small Signal)
4
–3 dB Bandwidth (Large Signal)
0.1 dB Bandwidth
4, 5
Slew Rate
Settling Time to 0.1%
AD8184AR
AD8184AR
AD8184AR
Conditions
Channel-to-Channel
IN0 = +1 V, IN1 = –1 V
A0, A1
=
0 or 1
IN0 = +1 V, –1 V or IN1 = –1 V, +1 V
A0, A1 = 0 or 1
IN1 = +1 V, –1 V or IN1 = –1 V, +1 V
All Inputs Are Grounded
A0, A1 and
ENABLE
Inputs
A0, A1 and
ENABLE
Inputs
A0, A1,
ENABLE
= +4 V
A0, A1,
ENABLE
= +0.4 V
V
IN
= 50 mV rms, R
L
= 5 kΩ
V
IN
= 1 V rms, R
L
= 5 kΩ
V
IN
= 50 mV rms, R
L
= 5 kΩ
2 V Step
2 V Step
ƒ = 3.58 MHz, R
L
= 2 kΩ
f
= 3.58 MHz,
R
L
= 10 kΩ
f
= 3.58 MHz, R
L
= 2 kΩ
f
= 3.58 MHz,
R
L
= 10 kΩ
ƒ = 5 MHz
ƒ = 30 MHz
ƒ = 5 MHz, R
L
= 30
Ω
ƒ = 30 MHz
ƒ
C
= 10 MHz, V
O
= 2 V p-p, R
L
= 1 kΩ
V
IN
=
±
1 V
T
MIN
to T
MAX
5
10
15
12
22
±
25
2.0
10
2
550
105
60
600
700
135
75
750
15
0.2
0.01
0.2
0.01
–95
–78
–115
4.5
–74
0.982
2
5
0.6
2.5
5
1.0
2.4
1.6
1.6
±
3.3
±
3.2
30
28
10
3.2
0.8
200
3
ns
ns
ns
ns
ns
mV
V
V
nA
µA
MHz
MHz
MHz
V/µs
ns
%
%
Degrees
Degrees
dB
dB
dB
nV/√Hz
dBc
V/V
mV
mV
µV/°C
mV
µA
µA
nA/°C
MΩ
pF
pF
V
V
mA
Ω
MΩ
pF
V
dB
dB
mA
mA
mA
mA
°C
DISTORTION/NOISE PERFORMANCE
Differential Gain
Differential Phase
All Hostile Crosstalk
6
OFF Isolation
7
Voltage Noise
Total Harmonic Distortion
AD8184AR
AD8184AR
0.02
0.02
DC/TRANSFER CHARACTERISTICS
Voltage Gain
8
Input Offset Voltage
Input Offset Voltage Drift
Input Offset Voltage Matching
Input Bias Current
Input Bias Current Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Current
Output Resistance
Output Capacitance
POWER SUPPLY
Operating Range
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Quiescent Current
8
15
3
7.5
9.5
Channel-to-Channel
T
MIN
to T
MAX
Channel Enabled (R Package)
Channel Disabled (R Package)
V
IN
=
±
4 V, R
L
= 2 kΩ
9
Enabled
Disabled
Disabled (R Package)
±
3.15
33
+PSRR
–PSRR
+V
S
= +4.5 V to +5.5 V, –V
S
= –5 V
–V
S
= –4.5 V to –5.5 V, +V
S
= +5 V
Enabled
T
MIN
to T
MAX
Disabled
T
MIN
to T
MAX
±
4
54
51
±
6
57
54
4.4
2.1
5.2
5.7
2.9
2.9
+85
OPERATING TEMPERATURE RANGE
–40
–2–
REV. 0
AD8184
NOTES
1
ENABLE
pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = –1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0
input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa. All inputs are measured in a similar
manner using A0 and A1 to select the channels.
2
ENABLE
pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activated (refer to Table I). Set IN0 and IN2 = +1 V dc,
IN1 and IN3 = –1 V dc, and measure transition time from 50% of
ENABLE
pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4,
∆t
OFF
is the disable time,
∆t
ON
is the enable time.
3
All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing R
L
.
4
Decreasing R
L
slightly lowers the bandwidth. Increasing C
L
significantly lowers the bandwidth (see Figure 18).
5
A resistor (R
S
) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.)
6
Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with V
IN
= 0.707 V rms and monitor the output at ƒ = 5 and 30 MHz.
R
L
= 2 kΩ (see Figure 12).
7
Multiplexer is disabled (i.e.,
ENABLE
= logic 1) and all inputs are driven simultaneously with V
IN
= 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. R
L
= 30
Ω
to simu-
late R
ON
of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the
load impedance determines the crosstalk.
8
Voltage gain decreases for lower values of R
L
. The resistive divider formed by the multiplexers enables output resistance (28
Ω)
and R
L
causes a gain that increases as R
L-
decreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for R
L
= 1 kΩ).
9
Larger values of R
L
provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 14-pin plastic package:
θ
JA
= 75°C/Watt
14-pin SOIC package:
θ
JA
= 120°C/Watt, where P
D
= (T
J
–T
A
)/θ
JA
.
MAXIMUM POWER DISSIPATION – Watts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V
Internal Power Dissipation
2
AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts
AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
V
S
Output Short Circuit Duration . . Observe Power Derating Curves
Storage Temperature Range
N & R Package . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C
While the AD8184 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tempera-
ture (+150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves shown in Figure 2.
2.5
T
J
= +150°C
2.0
14-PIN DIP PACKAGE
1.5
14-PIN SOIC
1.0
ORDERING GUIDE
Model
AD8184AN
AD8184AR
AD8184AR-REEL
AD8184-EB
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Package
Description
Package
Option
14-Lead Plastic DIP N-14
14-Lead Narrow SOIC R-14
Reel 14-Lead SOIC
R-14
For AD8184R
0.5
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE –
°C
80 90
Figure 2. Maximum Power Dissipation vs. Temperature
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8184
is limited by the associated rise in junction temperature. The maxi-
mum safe junction temperature for plastic encapsulated devices is
determined by the glass transition temperature of the plastic,
approximately +150°C. Exceeding this limit temporarily may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of +175°C for an extended period can result in
device failure.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8184–Typical Performance Curves
5
DUT OUT
500mV/DIV
4
3
A0 PULSE
0 TO 5V
V
IN
= 50mVrms
R
L
= 5kΩ
R
S
= 0Ω
NORMALIZED OUTPUT – dB
2
1
0
–1
–2
–3
–4
1V
OUTPUT
–1V
5ns/DIV
–5
1M
10M
100M
FREQUENCY – Hz
1G
Figure 3 Channel Switching Characteristics
Figure 6. Small Signal Frequency Response
0.5
0.4
NORMALIZED FLATNESS – dB
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
V
IN
= 50mVrms
R
L
= 5kΩ
R
S
= 0Ω
+1V
DUT OUT
800mV/DIV
–1V
+1V
PULSE
0 TO 5V
–1V
t
OFF
t
ON
10ns/DIV
–0.5
1M
10M
100M
FREQUENCY – Hz
1G
Figure 4. Enable and Disable Switching Characteristics
Figure 7. Gain Flatness vs. Frequency
3
R
L
= 5kΩ
0
OUTPUT
SWITCHING A0
25mV/DIV
V
IN
= 1.0Vrms
–3
–6
OUTPUT – dBV
V
IN
= 0.5Vrms
–9
–12
–15
–18
V
IN
= 125mVrms
V
IN
= 0.25Vrms
OUTPUT
SWITCHING A1
A0 and A1 PULSE
0 TO +5V
–21
–24
V
IN
= 62.5mVrms
25ns/DIV
–27
1M
10M
100M
FREQUENCY – Hz
1G
Figure 5. Channel Switching Transient (Glitch)
Figure 8. Large Signal Frequency Response
–4–
REV. 0
