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Data Sheet
FEATURES
Single 3 V supply operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist)
SFDR = 77 dBc (to Nyquist)
Low power ADC core: 96 mW at 65 MSPS, 104 mW
@ 80 MSPS, 120 mW at 105 MSPS
Differential input with 300 MHz bandwidth
On-chip reference and sample-and-hold amplifier
DNL = ±0.25 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
VIN+
10-Bit, 65/80/105 MSPS,
3 V A/D Converter
AD9215
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
SHA
VIN–
REFT
REFB
PIPELINE
ADC CORE
AD9215
CORRECTION LOGIC
10
OUTPUT BUFFERS
OR
D9 (MSB)
VREF
SENSE
REF
SELECT
0.5V
CLOCK
DUTY CYCLE
STABLIZER
MODE
SELECT
D0
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
AGND
CLK
PDWN
MODE DGND
Figure 1.
PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit,
65/80/105 MSPS analog-to-digital converters (ADC). This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9215 uses a multistage differential
pipelined architecture with output error correction logic to pro-
vide 10-bit accuracy at 105 MSPS data rates and to guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential sample-and-hold ampli-
fier (SHA) allows for a variety of user-selectable input ranges
and offsets including single-ended applications. It is suitable for
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling single-channel inputs at
frequencies well beyond the Nyquist rate. Combined with pow-
er and cost savings over previously available ADCs, the AD9215
is suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer compensates for wide variations in the
clock duty cycle while maintaining excellent performance. The digital
output data is presented in straight binary or twos complement for-
mats. An out-of-range signal indicates an overflow condition, which
can be used with the MSB to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9215 is avail-
able in both a 28-lead surface-mount plastic package and a
32-lead chip scale package and is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
The AD9215 operates from a single 3 V power supply and
features a separate digital output driver supply to accom-
modate 2.5 V and 3.3 V logic families.
Operating at 105 MSPS, the AD9215 core ADC consumes
a low 120 mW; at 80 MSPS, the power dissipation is 104
mW; and at 65 MSPS, the power dissipation is 96 mW.
The patented SHA input maintains excellent performance
for input frequencies up to 200 MHz and can be config-
ured for single-ended or differential operation.
The AD9215 is part of several pin compatible 10-, 12-, and
14-bit low power ADCs. This allows a simplified upgrade
from 10 bits to 12 bits for systems up to 80 MSPS.
The clock duty cycle stabilizer maintains converter per-
formance over a wide range of clock pulse widths.
The out of range (OR) output bit indicates when the signal
is beyond the selected input range.
2.
3.
4.
5.
6.
Rev. B
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Trademarks and registered trademarks are the property of their respective owners.
02874-A-001
AD9215
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings
1
.......................................................... 6
Explanation of Test Levels ........................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Equivalent Circuits ....................................................................... 8
Definitions of Specifications ....................................................... 8
Typical Performance Characteristics ........................................... 10
Applying the AD9215 Theory of Operation ............................... 14
Clock Input and Considerations .............................................. 15
Evaluation Board ........................................................................ 18
Outline Dimensions ....................................................................... 33
Ordering Guide........................................................................... 34
Data Sheet
REVISION HISTORY
2/13—Data Sheet Changed from a REV. A to a REV. B
Changes to Figure 4 and Added EPAD Note to Pin Configura-
tions and Function Descriptions Section ..................................... 7
Changes to Voltage Reference Section........................................ 17
Changes to Evaluation Board Section......................................... 18
Updated Outline Dimensions ...................................................... 33
Changes to Ordering Guide ......................................................... 34
2/04—Data Sheet Changed from a REV. 0 to a REV. A
Renumbered Figures and Tables ..............................UNIVERSAL
Changes to Product Title ................................................................ 1
Changes to Features ........................................................................ 1
Changes to Product Description ................................................... 1
Changes to Product Highlights ..................................................... 1
Changes to Specifications ............................................................... 2
Changes to Figure 2 ......................................................................... 4
Changes to Figures 9 to 11 ........................................................... 10
Added Figure 14 ............................................................................ 10
Added Figures 16 and 18 .............................................................. 11
Changes to Figures 21 to 24 and 25 to 26................................... 12
Deleted Figure 25........................................................................... 12
Changes to Figures 28 and 29 ...................................................... 13
Changes to Figure 31..................................................................... 14
Changes t0 Figure 35 ..................................................................... 16
Changes to Figures 50 through 58............................................... 26
Added Table 11 .............................................................................. 31
Updated Outline Dimensions ...................................................... 32
Changes to Ordering Guide ......................................................... 33
5/03—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
SPECIFICATIONS
AD9215
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise
noted.
Table 1. DC Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
1
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
1
Gain Error
1
Reference Voltage (1 V Mode)
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
I
AVDD2
I
DRVDD2
PSRR
POWER CONSUMPTION
Sine Wave Input
2
I
AVDD2
I
DRVDD2
Standby Power
4
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Test
Level
VI
VI
VI
VI
VI
VI
V
V
V
VI
V
V
V
V
V
IV
IV
V
V
Min
10
Typ
Max
AD9215BRU-80/
AD9215BCP-80
Min
10
Typ
Max
AD9215BRU-105/
AD9215BCP-105
Min
10
Typ
Max
Unit
Bits
Guaranteed
±0.3
±2.0
0
+1.5
+4.0
−1.0 ±0.5
+1.0
±0.5
±1.2
+15
+30
±230
±2
0.2
±1
0.2
0.8
0.4
1
2
2
7
±35
Guaranteed
±0.3
±2.0
+1.5
+4.0
−1.0 ±0.5
+1.0
±0.5
±1.2
+15
+30
±230
±2
0.2
±1
0.2
0.8
0.4
1
2
2
7
±35
Guaranteed
±0.3
±2.0
+1.5
+4.0
−1.0
±0.6
+1.2
±0.65 ±1.2
+15
+30
±230
±2
0.2
±1
0.2
0.8
0.4
1
2
2
7
±35
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
Full
Full
Full
25°C
Full
IV
IV
VI
V
V
2.7
2.25
3.0
2.5
32
7.0
± 0.1
3.3
3.6
35
2.7
2.25
3.0
2.5
34.5
8.6
± 0.1
3.3
3.6
39
2.7
2.25
3.0
2.5
40
11.3
± 0.1
3.3
3.6
44
V
V
mA
mA
% FSR
Full
25°C
25°C
VI
V
V
96
18
1.0
104
20
1.0
120
25
1.0
mW
mW
mW
With a 1.0 V internal reference.
Measured at f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
1
2
Rev. B | Page 3 of 36
AD9215
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.
Table 2. AC Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 2.4 MHz
f
IN
= Nyquist
1
Data Sheet
AD9215BRU-80/
AD9215BCP-80
Min
56.0
57.0
56.0
56.5
Typ
58.5
59.0
58.0
58.5
58.0
57.5
58.5
58.5
58.0
58.5
56.0
55.5
9.5
9.5
9.4
9.5
9.1
9.0
−78
−80
−76
−78
−70
−70
−77
−77
−77
−77
−80
−80
75
74
300
−64
−65
−63
−65
Max
AD9215BRU-105/
AD9215BCP-105
Min
Typ
57.5
58.5
57.5
58.0
57.8
57.7
57.6
58.2
57.3
57.8
57.7
57.4
9.3
9.5
9.4
9.4
9.4
9.3
−78
−84
−74
−75
−75
−74
−73
−75
−71
−75
-75
−75
75
74
300
Max
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
Temp
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Test
Level
VI
I
VI
I
V
V
VI
I
VI
I
V
V
VI
I
VI
I
V
V
VI
I
VI
I
V
V
VI
I
VI
I
V
V
V
V
V
Min
56.0
57.0
56.0
56.5
Typ
58.5
59.0
58.0
58.5
Max
56.6
56.4
f
IN
= 70 MHz
f
IN
= 100 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 2.4 MHz
f
IN
= Nyquist
1
55.8
56.5
55.8
56.3
58.5
59.0
58.0
58.5
55.7
56.8
55.5
56.3
56.5
56.1
f
IN
= 70 MHz
f
IN
= 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 2.4 MHz
f
IN
= Nyquist
1
9.1
9.2
9.1
9.1
9.5
9.6
9.4
9.5
9.0
9.3
9.0
9.0
9.2
9.1
f
IN
= 70 MHz
f
IN
= 100 MHz
WORST HARMONIC (Second or Third)
f
IN
= 2.4 MHz
f
IN
= Nyquist
1
f
IN
= 70 MHz
f
IN
= 100 MHz
WORST OTHER (Excluding Second or Third)
f
IN
= 2.4 MHz
f
IN
= Nyquist
1
f
IN
= 70 MHz
f
IN
= 100 MHz
TWO-TONE SFDR (AIN = –7 dBFS)
f
IN1
= 70.3 MHz, f
IN2
= 71.3 MHz
f
IN1
= 100.3 MHz, f
IN2
= 101.3 MHz
ANALOG BANDWIDTH
−78
−80
−77
−78
−64
−65
−64
−65
−70
−61
−77
−78
−77
−78
−67
−68
−67
−68
−66
−68
−66
−68
−66
−63
300
1
Tested at f
IN
= 35 MHz for AD9215-65; f
IN
= 39 MHz for AD9215-80; and f
IN
= 50 MHz for AD9215-105.
Rev. B | Page 4 of 36
