Complete 12-Bit, 25 MSPS
Monolithic A/D Converter
AD9225
FEATURES
Monolithic 12-Bit, 25 MSPS ADC
Low Power Dissipation: 280 mW
Single 5 V Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.4 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 71 dB
Spurious-Free Dynamic Range: –85 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC
28-Lead SSOP
Compatible with 3 V Logic
FUNCTIONAL BLOCK DIAGRAM
CLK
SHA
VINA
VINB
CAPT
CAPB
VREF
SENSE
MODE
SELECT
1V
MDAC1
GAIN = 16
ADC
MDAC2
GAIN = 4
ADC
MDAC3
GAIN = 4
ADC
AVDD
DRVDD
5
3
3
ADC
5
3
12
OUTPUT BUFFERS
3
4
DIGITAL CORRECTION LOGIC
OTR
BIT 1
(MSB)
BIT 12
(LSB)
AD9225
REFCOM
AVSS
DRVSS
CML
GENERAL DESCRIPTION
The AD9225 is a monolithic, single-supply, 12-bit, 25 MSPS
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier and voltage reference. The AD9225
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 25 MSPS
data rates, and guarantees no missing codes over the full operat-
ing temperature range.
The AD9225 combines a low cost, high speed CMOS process
and a novel architecture to achieve the resolution and speed of
existing bipolar implementations at a fraction of the power
consumption and cost.
The input of the AD9225 allows for easy interfacing to both
imaging and communications systems. With the device’s truly
differential input structure, the user can select a variety of input
ranges and offsets, including single-ended applications. The
dynamic performance is excellent.
The sample-and-hold amplifier (SHA) is well suited for both
multiplexed systems that switch full-scale voltage levels in succes-
sive channels and sampling single-channel inputs at frequencies
up to and well beyond the Nyquist rate.
The AD9225’s wideband input, combined with the power and
cost savings over previously available monolithics, suits applica-
tions in communications, imaging, and medical ultrasound.
The AD9225 has an on-board programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of an application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal indicates an overflow
condition that can be used with the most significant bit to deter-
mine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9225 is fabricated on a very cost effective CMOS pro-
cess. High speed precision analog circuits are combined with
high density logic circuits.
The AD9225 offers a complete, single-chip sampling, 12-bit,
25 MSPS analog-to-digital conversion function in 28-lead
SOIC and SSOP packages.
Low Power—The
AD9225 at 280 mW consumes a fraction of
the power presently available in monolithic solutions.
On-Board Sample-and-Hold Amplifier (SHA)—The
versa-
tile SHA input can be configured for either single-ended or
differential inputs.
Out-of-Range (OTR)—The
OTR output bit indicates when
the input signal is beyond the AD9225’s input range.
Single Supply—The
AD9225 uses a single 5 V power supply,
simplifying system power supply design. It also features a sepa-
rate digital driven supply line to accommodate 3 V and 5 V logic
families.
Pin Compatibility—The
AD9225 is pin compatible with the
AD9220, AD9221, AD9223, and AD9224 ADCs.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9225–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
RESOLUTION
MAX CONVERSION RATE
INPUT REFERRED NOISE
VREF = 1.0 V
VREF = 2.0 V
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
Zero Error (@ 25∞C)
Gain Error (@ 25∞C)
1
Gain Error (@ 25∞C)
2
TEMPERATURE DRIFT
Zero Error
Gain Error
1
Gain Error
2
POWER SUPPLY REJECTION
AVDD (+5 V
±
0.25 V)
ANALOG INPUT
Input Span
Input (VINA or VINB) Range
Input Capacitance
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.0 V Mode)
Output Voltage Tolerance (2.0 V Mode)
Output Current (Available for External Loads)
Load Regulation
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Currents
IAVDD
IDRVDD
POWER CONSUMPTION
External Reference
Internal Reference
NOTES
1
Includes internal voltage reference error.
2
Excludes internal voltage reference error.
3
Load regulation with 1 mA load current (in addition to that required by the AD9225).
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 5 V, f
SAMPLE
= 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T
MIN
to T
MAX
,
unless otherwise noted.)
Min
12
25
0.35
0.17
±
1.0
±
0.4
12
±
0.3
±
0.5
±
0.4
±
2
±
26
±
0.4
±
0.1
2
4
0
AVDD
10
1.0
±
5
2.0
±
10
1.0
1.0
8
±
0.35
±
2.5
±
1.0
±
0.6
±
2.2
±
1.7
Typ
Max
Unit
Bits
MHz
LSB rms
LSB rms
LSB
LSB
Bits Guaranteed
% FSR
% FSR
% FSR
ppm/∞C
ppm/∞C
ppm/∞C
% FSR
V p-p
V p-p
V
V
pF
V
mV
V
mV
mA
mV
kW
±
17
±
35
3.4
4.75
2.85
5
5.25
5.25
72.5
4.0
310
373
V (± 5% AVDD Operating)
V (± 5% DRVDD Operating)
mA
mA
mW (VREF = 1 V)
mW (VREF = 2 V)
mW (VREF = 1 V)
mW (VREF = 2 V)
65
2.0
280
335
290
345
–2–
REV. B
AD9225
AC SPECIFICATIONS
Parameter
(AVDD = 5 V, DRVDD = 5 V, f
SAMPLE
= 25 MSPS, VREF = 2.0 V, T
MIN
to T
MAX
, Differential Input unless
otherwise noted.)
Min
Typ
70.7
69.6
71
70
–82
–81
73
72.5
–85
–83
105
105
1
1
10
–72
–71.5
Max
Unit
dB
dB
dB
dB
dB
dB
dB
dB
MHz
MHz
ns
ps rms
ns
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT
= 2.5 MHz
67.4
f
INPUT
= 10 MHz
66.7
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
TOTAL HARMONIC DISTORTION (THD)
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
SPURIOUS FREE DYNAMIC RANGE
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
Full Power Bandwidth
Small Signal Bandwidth
Aperture Delay
Aperture Jitter
Acquisition to Full-Scale Step
Specifications subject to change without notice.
69.0
68.2
DIGITAL SPECIFICATIONS
Parameter
(AVDD = 5 V, DRVDD = 5 V, unless otherwise noted.)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OH
V
OL
V
OL
C
OUT
V
OH
V
OH
V
OL
V
OL
Min
3.5
–10
–10
5
4.5
2.4
0.4
0.1
5
2.95
2.80
0.4
0.05
1.0
+10
+10
Typ
Max
Unit
V
V
mA
mA
pF
V
V
V
V
pF
V
V
V
V
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= DRVDD)
Low Level Input Current (V
IN
= 0 V)
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage (I
OH
= 50
mA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
mA)
Output Capacitance
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50
mA)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
mA)
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameter
Clock Period*
CLOCK Pulse Width High
CLOCK Pulse Width Low
Output Delay
Pipeline Delay (Latency)
Specifications subject to change without notice.
(T
MIN
to T
MAX
with AVDD = 5 V, DRVDD = 5 V, C
L
= 20 pF)
Symbol
t
C
t
CH
t
CL
t
OD
Min
40
18
18
13
3
Typ
Max
Unit
ns
ns
ns
ns
Clock Cycles
*The
clock period may be extended to 1 ms without degradation in specified performance @ 25
∞C.
REV. B
–3–
AD9225
ABSOLUTE MAXIMUM RATINGS*
Pin Name
AVDD
DRVDD
AVSS
AVDD
REFCOM
CLK
Digital Outputs
VINA, VINB
VREF
SENSE
CAPB, CAPT
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With
Respect to
AVSS
DRVSS
DRVSS
DRVDD
AVSS
AVSS
DRVSS
AVSS
AVSS
AVSS
AVSS
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
+0.3
AVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
+150
300
Unit
V
V
V
V
V
V
V
V
V
V
V
∞C
∞C
∞C
*Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods
may affect device reliability.
S1
ANALOG
INPUT
S2
t
CH
t
C
S4
t
CL
S3
PIN CONFIGURATION
28-Lead SOIC and SSOP
INPUT
CLOCK
t
OD
DATA
OUTPUT
DATA 1
CLK
1
(LSB) BIT 12
2
BIT 11
3
BIT 10
4
28
27
26
25
24
DRVDD
DRVSS
AVDD
AVSS
VINB
VINA
Figure 1. Timing Diagram
BIT 9
5
BIT 8
6
BIT 7
7
AD9225
23
TOP VIEW
22
CML
(Not to Scale)
BIT 6
8
21
CAPT
BIT 5
9
20
19
18
17
16
15
CAPB
REFCOM
VREF
SENSE
AVSS
AVDD
BIT 4
10
BIT 3
11
BIT 2
12
(MSB) BIT 1
13
OTR
14
ORDERING GUIDE
Model
AD9225AR
AD9225ARRL
AD9225ARS
AD9225ARSRL
AD9225-EB
Temperature Range
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
Package Description
28-Lead Wide Body Small Outline
28-Lead Wide Body Small Outline
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
Evaluation Board
Package Option
R-28
R-28
RS-28
RS-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. B
AD9225
PIN FUNCTION DESCRIPTIONS
Pin Number
1
2
3–12
13
14
15, 26
16, 25
17
18
19
20
21
22
23
24
27
28
Mnemonic
CLK
BIT 12
BIT 11–2
BIT 1
OTR
AVDD
AVSS
SENSE
VREF
REFCOM
CAPB
CAPT
CML
VINA
VINB
DRVSS
DRVDD
Description
Clock Input Pin
Least Significant Data Bit (LSB)
Data Output Bit
Most Significant Data Bit (MSB)
Out of Range
5 V Analog Supply
Analog Ground
Reference Select
Input Span Select (Reference I/O)
Reference Common (AVSS)
Noise Reduction Pin
Noise Reduction Pin
Common-Mode Level (Midsupply)
Analog Input Pin (+)
Analog Input Pin (–)
Digital Output Driver Ground
3 V to 5 V Digital Output Driver Supply
TERMINOLOGY
Integral Nonlinearity (INL)
Aperture Delay
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Signal-to-Noise and Distortion Ratio (S/N+D, SINAD)
S/N+D is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
Zero Error
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N
= (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as
N,
the effective number of bits.
The effective number of bits for a device for sine wave inputs at
a given input frequency can be calculated directly from its mea-
sured SINAD.
Total Harmonic Distortion (THD)
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Temperature Drift
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25∞C) value to the value at
T
MIN
or T
MAX
.
Power Supply Rejection
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
Aperture Jitter
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the ADC.
REV. B
–5–
模拟电子
