14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9258
FEATURES
SNR = 77.6 dBFS @ 70 MHz and 125 MSPS
SFDR = 88 dBc @ 70 MHz and 125 MSPS
Low power: 750 mW @ 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−152.8 dBm/Hz small signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO/ SCLK/
DCS
DFS
CSB
DRVDD
AD9258
SPI
PROGRAMMING DATA
VIN+A
ADC
VIN–A
14
CMOS/LVDS
OUTPUT BUFFER
ORA
D13A (MSB)
TO
D0A (LSB)
CLK+
CLK–
VREF
SENSE
REF
SELECT
VCM
RBIAS
VIN–B
ADC
VIN+B
MULTICHIP
SYNC
DIVIDE 1
TO 8
DUTY CYCLE
STABILIZER
DCO
GENERATION
DCOA
DCOB
ORB
14
CMOS/LVDS
OUTPUT BUFFER
D13B (MSB)
TO
D0B (LSB)
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
AGND
SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
On-chip dither option for improved SFDR performance
with low power analog input.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
Pin compatibility with the AD9268, allowing a simple
migration from 14 bits to 16 bits. The AD9258 is also pin
compatible with the
AD9251, AD9231,
and
AD9204
family
of products for lower sample rate, low power applications.
4.
5.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
08124-001
AD9258
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
ADC DC Specifications ................................................................. 4
ADC AC Specifications ................................................................. 6
Digital Specifications ................................................................... 7
Switching Specifications ................................................................ 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings.......................................................... 12
Thermal Characteristics ............................................................ 12
ESD Caution ................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 17
Equivalent Circuits ......................................................................... 25
Theory of Operation ...................................................................... 26
ADC Architecture ...................................................................... 26
Analog Input Considerations.................................................... 26
Voltage Reference ....................................................................... 29
Clock Input Considerations ...................................................... 30
Channel/Chip Synchronization ................................................ 31
Power Dissipation and Standby Mode .................................... 32
Digital Outputs ........................................................................... 32
Timing ......................................................................................... 33
Built-In Self-Test (BIST) and Output Test .................................. 34
Built-In Self-Test (BIST) ............................................................ 34
Output Test Modes ..................................................................... 34
Serial Port Interface (SPI) .............................................................. 35
Configuration Using the SPI ..................................................... 35
Hardware Interface..................................................................... 36
Configuration Without the SPI ................................................ 36
SPI Accessible Features .............................................................. 36
Memory Map .................................................................................. 37
Reading the Memory Map Register Table............................... 37
Memory Map Register Table ..................................................... 38
Memory Map Register Descriptions ........................................ 40
Applications Information .............................................................. 41
Design Guidelines ...................................................................... 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
9/09—Rev. 0 to Rev. A
Changes to Features List .................................................................. 1
Changes to Specifications Section .................................................. 4
Changes to Table 5 ............................................................................ 9
Changes to Typical Performance Characteristics Section ......... 17
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 44
AD9258
GENERAL DESCRIPTION
The AD9258 is a dual, 14-bit, 80 MSPS/105 MSPS/125 MSPS
analog-to-digital converter (ADC). The AD9258 is designed to
support communications applications where high performance,
combined with low cost, small size, and versatility, is desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases design consid-
erations. A duty cycle stabilizer is provided to compensate for
variations in the ADC clock duty cycle, allowing the converters
to maintain excellent performance.
The ADC output data can be routed directly to the two external
14-bit output ports. These outputs can be set to either 1.8 V CMOS
or LVDS.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9258 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
Rev. A | Page 3 of 44
AD9258
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential
Nonlinearity (DNL)
1
Integral Nonlinearity
(INL)
1
MATCHING
CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error
(1 V Mode)
Load Regulation @
1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF =
1.0 V
Input Capacitance
2
Input Common-
Mode Voltage
REFERENCE INPUT
RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
1
IDRVDD
1
(1.8 V
CMOS)
IDRVDD
1
(1.8 V
LVDS)
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
AD9258BCPZ-80
Min Typ
Max
14
Guaranteed
±0.1
±0.4
AD9258BCPZ-105
Min Typ
Max
14
Guaranteed
±0.1
±0.4
AD9258BCPZ-125
Min Typ
Max
14
Guaranteed
±0.4
±0.4
Unit
Bits
±0.5
±2.5
±0.5
±0.5
±2.5
±0.5
±0.65
±2.5
±0.5
% FSR
% FSR
LSB
LSB
LSB
LSB
±0.25
±1.1
±0.55
±0.25
±1.3
±0.7
±0.25
±1.4
±0.8
Full
Full
Full
Full
±0.1
±0.3
±2
±15
±0.4
±1.3
±0.1
±0.3
±2
±15
±0.4
±1.3
±0.2
±0.3
±2
±15
±0.45
±1.3
% FSR
% FSR
ppm/°C
ppm/°C
Full
Full
±5
5
±12
±5
5
±12
±5
5
±12
mV
mV
25°C
0.62
0.63
0.7
LSB
rms
V p-p
pF
V
kΩ
Full
Full
Full
Full
2
8
0.9
6
2
8
0.9
6
2
8
0.9
6
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.8
234
33
81
1.9
1.9
240
1.7
1.7
1.8
1.8
293
43
81
1.9
1.9
300
1.7
1.7
1.8
1.8
390
53
90
1.9
1.9
400
V
V
mA
mA
mA
Rev. A | Page 4 of 44
AD9258
Parameter
POWER CONSUMPTION
DC Input
Sine Wave Input
1
(DRVDD = 1.8 V
CMOS Output
Mode)
Sine Wave Input
1
(DRVDD = 1.8 V
LVDS Output
Mode)
Standby Power
3
Power-Down Power
1
2
Temperature
Full
Full
AD9258BCPZ-80
Min Typ
Max
462
481
487
AD9258BCPZ-105
Min Typ
Max
565
605
590
AD9258BCPZ-125
Min Typ
Max
750
797
777
Unit
mW
mW
Full
568
671
865
mW
Full
Full
45
0.5
2.5
45
0.5
2.5
45
0.5
2.5
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Rev. A | Page 5 of 44
ARM技术
