Data Sheet
FEATURES
Dual, Low Power, 8-/10-/12-/14-Bit
TxDAC Digital-to-Analog Converters
AD9714/AD9715/AD9716/AD9717
GENERAL DESCRIPTION
The AD9714/AD9715/AD9716/AD9717 are pin-compatible,
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of commu-
nication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9714/AD9715/AD9716/AD9717
make them well-suited for portable and low power applications.
Power dissipation @ 3.3 V, 2 mA output
37 mW @ 10 MSPS
86 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
84 dBc @ 1 MHz output
75 dBc @ 10 MHz output
AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz
Differential current outputs: 1 mA to 4 mA
2 on-chip auxiliary DACs
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package
PRODUCT HIGHLIGHTS
1.
Low Power.
DACs operate on a single 1.8 V to 3.3 V supply; total power
consumption reduces to 35 mW at 125 MSPS with a 1.8 V
supply. Sleep and power-down modes are provided for low
power idle periods.
CMOS Clock Input.
High speed, single-ended CMOS clock input supports a
125 MSPS conversion rate.
Easy Interfacing to Other Components.
Adjustable output common mode from 0 V to 1.2 V allows
easy interfacing to other components that accept common-
mode levels greater than 0 V.
APPLICATIONS
Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
2.
3.
Rev. B
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AD9714/AD9715/AD9716/AD9717
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 7
AC Specifications.......................................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 31
Theory of Operation ...................................................................... 32
Serial Peripheral Interface (SPI) ................................................... 33
General Operation of the Serial Interface ............................... 33
Instruction Byte .......................................................................... 33
Serial Interface Port Pin Descriptions ..................................... 33
MSB/LSB Transfers..................................................................... 34
Serial Port Operation ................................................................. 34
Pin Mode ..................................................................................... 34
SPI Register Map ............................................................................. 35
SPI Register Descriptions .............................................................. 36
Digital Interface Operation ........................................................... 40
Digital Data Latching and Retimer Block ............................... 41
Data Sheet
Estimating the Overall DAC Pipeline Delay........................... 42
Reference Operation .................................................................. 43
Reference Control Amplifier .................................................... 43
DAC Transfer Function ............................................................. 44
Analog Output ............................................................................ 44
Self-Calibration........................................................................... 45
Coarse Gain Adjustment ........................................................... 46
Using the Internal Termination Resistors ............................... 47
Applications Information .............................................................. 48
Output Configurations .............................................................. 48
Differential Coupling Using a Transformer ............................... 48
Single-Ended Buffered Output Using an Op Amp ................ 48
Differential Buffered Output Using an Op Amp ................... 49
Auxiliary DACs........................................................................... 49
DAC-to-Modulator Interfacing ................................................ 50
Correcting for Nonideal Performance of Quadrature
Modulators on the IF-to-RF Conversion ................................ 50
I/Q-Channel Gain Matching .................................................... 50
LO Feedthrough Compensation .............................................. 51
Results of Gain and Offset Correction .................................... 51
Modifying the Evaluation Board to Use the ADL5370 On-
Board Quadrature Modulator................................................... 52
Evaluation Board Shematics and Artwork .................................. 53
Schematics ................................................................................... 53
Silkscreens ................................................................................... 61
Bill of Materials ............................................................................... 76
Outline Dimensions ....................................................................... 79
Ordering Guide .......................................................................... 79
Rev. B | Page 2 of 80
Data Sheet
REVISION HISTORY
1/2018—Rev. A to Rev. B
Changes to Figure 94 ......................................................................41
Changes to Estimating the Overall DAC Pipeline Section ........42
Changes to Ordering Guide ...........................................................79
3/2009—Rev. 0 to Rev. A
Changes to Figure 1........................................................................... 4
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Table 1 Conditions ............................................................................ 5
Changes to Table 1 ............................................................................ 5
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Table 2 Conditions ............................................................................ 7
Changed DVDD = 3.3 V to DVDD = 1.8 V, and DVDDIO = 1.8 V
to DVDDIO = 3.3 V, Table 3 Conditions ....................................... 8
Changed DVDD = 3.3 V to DVDD = 1.8 V, CVDD = 3.3 V to
CVDD = 1.8 V, Table 4 Conditions ................................................. 8
Changes to Table 5 and Table 6 ....................................................... 9
Changes to Figure 2 and Table 7 ...................................................10
Changes to Figure 3 and Table 8 ...................................................12
Changes to Figure 4 and Table 9 ...................................................14
Changes to Table 10 ........................................................................16
Changes to Typical Performance Characteristics Section .........18
Changes to Figure 84 and Theory of Operation Section ...........32
Added Figure 85 to Figure 88; Renumbered Sequentially .........34
Changes to Pin Mode Section........................................................35
AD9714/AD9715/AD9716/AD9717
Changes to Table 13 ........................................................................ 36
Changes to Table 14 ........................................................................ 37
Changes to Digital Interface Operation Section and Figure 89 to
Figure 93 ........................................................................................... 40
Changes to Digital Data Latching and Retimer Block Section,
Figure 94, and Retimer Section ..................................................... 41
Changes to Estimating the Overall DAC Pipeline Delay
Section .............................................................................................. 42
Added Reference Operation Section, Figure 96,
Recommendations When Using an External Reference Section,
and Reference Control Amplifier Section.................................... 43
Added Table 17; Renumbered Sequentially ................................. 43
Added DAC Transfer Function Section and Analog Output
Section .............................................................................................. 44
Changes to Figure 99 and Figure 100 ........................................... 46
Changes to Auxiliary DACs Section and Figure 107.................. 49
Changes to DAC-to-Modulator Interfacing Section and
Figure 108 ......................................................................................... 49
Changes to Figure 108 and Figure 109 ......................................... 50
Added Evaluation Board Schematics and Artwork Section, and
Figure 112 to Figure 134................................................................. 53
Added Bill of Materials Section and Table 18 ............................. 76
8/2008—Revision 0: Initial Version
Rev. B | Page 3 of 80
AD9714/AD9715/AD9716/AD9717
FUNCTIONAL BLOCK DIAGRAM
FSADJQ/AUXQ
SDIO/FORMAT
RESET/PINMD
SCLK/CLKMD
FSADJI/AUXI
DB13 (MSB)
CS/PWRDN
REFIO
DB12
CMLI
Data Sheet
1V
DB11
DB10
DB9
DB8
DVDDIO
DVSS
DVDD
DB7
DB6
DB5
CLOCK
DIST
1.8V
LDO
I
REF
100µA
BAND
GAP
1 INTO 2
INTERLEAVED
DATA
INTERFACE
I DATA
SPI
INTERFACE
QR
SET
16kΩ
10kΩ
AD9717
IR
SET
16kΩ
IR
CML
1kΩ TO
250Ω
RLIN
500Ω
IOUTN
IOUTP
500Ω
RLIP
AVDD
AVSS
RLQP
500Ω
I DAC
AUX1DAC
AUX2DAC
Q DATA
Q DAC
500Ω
QOUTP
QOUTN
RLQN
QR
CML
1kΩ TO
250Ω
DCLKIO
CLKIN
DB0 (LSB)
CMLQ
CVDD
CVSS
DB4
DB3
DB2
DB1
Figure 1.
Rev. B | Page 4 of 80
07265-001
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD9714/AD9715/AD9716/AD9717
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, I
xOUTFS
= 2 mA, maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY, AVDD = DVDDIO =
CVDD = 3.3 V
Differential Nonlinearity (DNL)
Precalibration
Postcalibration
Integral Nonlinearity (INL)
Precalibration
Postcalibration
ACCURACY, AVDD = DVDDIO =
CVDD = 1.8 V
Differential Nonlinearity (DNL)
Precalibration
Postcalibration
Integral Nonlinearity (INL)
Precalibration
Postcalibration
MAIN DAC OUTPUTS
Offset Error
Gain Error
Internal Reference
Full-Scale Output Current
1
AVDD = 3.3 V
AVDD = 1.8 V
Output Compliance Range
Output Resistance
Crosstalk, Q DAC to I DAC
f
OUT
= 30 MHz
f
OUT
= 60 MHz
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUXDAC OUTPUTS
Resolution
Full-Scale Output Current
(Current Sourcing Mode)
Voltage Output Mode
Output Compliance Range
(Sourcing 1 mA)
Output Compliance Range
(Sinking 1 mA)
Output Resistance in Current
Output Mode, AV
SS
to 1 V
AUX DAC Monotonicity
Guaranteed
REFERENCE OUTPUT
Internal Reference Voltage
Output Resistance
Min
AD9714
Typ
Max
8
Min
AD9715
Typ
Max
10
Min
AD9716
Typ
Max
12
Min
AD9717
Typ
Max
14
Unit
Bits
±0.02
±0.003
±0.025
±0.01
±0.08
±0.01
±0.13
±0.05
±0.4
±0.2
±0.4
±0.3
±1.7
±1.0
±1.8
±1.3
LSB
LSB
LSB
LSB
±0.02
±0.005
±0.025
±0.02
−1
−2
1
1
−0.5
2
2
0
200
97
78
0
±40
±25
10
125
V
SS
V
SS
V
SS
+
0.25
1
10
V
DD
V
DD
−
0.25
V
DD
V
SS
V
SS
V
SS
+
0.25
0
+1
+2
4
2.5
+1.2
−1
−2
1
1
−0.5
±0.08
±0.01
±0.12
±0.05
0
+1
+2
2
2
0
200
97
78
0
±40
±25
10
125
V
DD
V
DD
−
0.25
V
DD
1
10
V
SS
V
SS
V
SS
+
0.25
4
2.5
+1.2
−1
−2
1
1
−0.5
±0.4
±0.2
±0.4
±0.25
0
+1
+2
2
2
0
200
97
78
0
±40
±25
10
125
V
DD
V
DD
−
0.25
V
DD
1
10
V
SS
V
SS
V
SS
+
0.25
4
2.5
+1.2
−1
−2
1
1
−0.5
±1.2
±1.0
±1.5
±1.1
0
+1
+2
2
2
0
200
97
78
0
±40
±25
10
125
V
DD
V
DD
−
0.25
V
DD
1
10
4
2.5
+1.2
LSB
LSB
LSB
LSB
mV
% of FSR
mA
mA
V
MΩ
dB
dB
ppm/°C
ppm/°C
ppm/°C
Bits
µA
V
V
V
MΩ
Bits
0.98
1.025
10
1.08
0.98
1.025
10
1.08
0.98
1.025
10
1.08
0.98
1.025
10
1.08
V
kΩ
Rev. B | Page 5 of 80
