Typical rms noise at worst case transitions and temperatures.
3
Measured with fixed resistors as shown in Figure 5 (AD976) and Figure 6 (AD976A). Adjustable to zero as shown in Figure 7.
4
Full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage and includes the effect
of offset error. The full-scale error is the worst case of either the –full-scale or +full-scale code transition voltage errors.
5
f
IN
= 20 kHz (AD976) and f
IN
= 45 kHz (AD976A), 0.5 dB down, unless otherwise noted.
6
All specifications in dB are referred to a full scale
±
10 V input.
7
Full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy.
8
Recovers to specified performance after a 2
×
F
S
input overvoltage.
Specifications subject to change without notice.
–2–
REV. C
AD976/AD976A
AD976–SPECIFICATIONS
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Impedance
Capacitance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
2
Full-Scale Error
3, 4
Full-Scale Error Drift
Full-Scale Error, Ext. REF = 2.5 V
Full-Scale Error Drift, Ext. REF = 2.5 V
Bipolar Zero Error
4
Bipolar Zero Error Drift
Power Supply Sensitivity
V
ANA
= V
DIG
= V
D
= 5 V
±
5%
AC ACCURACY
Spurious Free Dynamic Range
5
Total Harmonic Distortion
5
Signal to (Noise + Distortion)
5
–60 dB Input
Signal to Noise
5
Full-Power Bandwidth
7
Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Transient Response
Full-Scale Step
Overvoltage Recovery
8
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
Ext. REF = 2.5 V
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
2.48
Min
16
(–40 C to +85 C, F
S
= 100 kHz, Ref = Internal Reference,
V
DIG
= V
ANA
= +5 V unless otherwise noted)
Max
Min
16
AD976B
Typ
Max
Min
16
±
10
23
22
10
10
100
±
3
+3
±
2
+1.75
1.0
±
7
±
2
±
2
±
0.25
±
0.25
±
10
±
8
96
–90
–96
85
83
28
85
83
700
1.5
40
2
2
150
2.52
2.48
2.5
1
2.5
2.52
2.48
150
2.5
1
2.5
2.52
700
1.5
40
2
27
90
–90
100
±
3
±
2
15
1.0
±
7
±
2
±
2
±
10
23
22
10
AD976C
Typ Max
Units
Bits
V
kΩ
pF
µs
kHz
LSB
1
LSB
Bit
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
LSB
dB
6
dB
dB
dB
dB
kHz
MHz
ns
µs
ns
V
µA
V
µA
AD976A
Typ
±
10
23
22
100
–2
15
1.0
±
7
±
2
±
2
–1
16
±
0.5
±
0.5
±
10
±
8
±
0.5
±
0.5
±
15
±
8
90
83
27
83
700
1.5
40
150
2.5
1
2.5
2.3
2.7
100
2.3
2.7
100
2.3
2.7
100
–0.3
+2.0
+0.8
V
DIG
+ 0.3
±
10
±
10
–0.3
+2.0
+0.8
V
DIG
+ 0.3
±
10
±
10
–0.3
+2.0
+0.8
V
DIG
+ 0.3
±
10
±
10
V
V
µA
µA
NOTES
1
LSB means least significant bit. With a
±
10 V input, one LSB is 305
µV.
2
Typical rms noise at worst case transitions and temperatures.
3
Measured with fixed resistors as shown in Figure 5 (AD976) and Figure 6 (AD976A). Adjustable to zero as shown in Figure 7.
4
Full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage and includes the effect
of offset error. The full-scale error is the worst case of either the –full-scale or +full-scale code transition voltage errors.
5
f
IN
= 20 kHz (AD976) and f
IN
= 45 kHz (AD976A), 0.5 dB down, unless otherwise noted.
6
All specifications in dB are referred to a full scale
±
10 V input.
7
Full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of accuracy.
8
Recovers to specified performance after a 2
×
F
S
input overvoltage.
Specifications subject to change without notice.
REV. C
–3–
AD976/AD976A
Parameter
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
V
OH
Leakage Current
Output Capacitance
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
POWER SUPPLIES
Specified Performance
V
DIG
V
ANA
I
DIG
I
ANA
Power Dissipation
TEMPERATURE RANGE
Specified Performance
Specifications subject to change without notice.
Conditions
Min
All Grades
Typ
Max
Units
I
SINK
= 1.6 mA
I
SOURCE
= 500
µA
High-Z State,
V
OUT
= 0 V to V
DIG
High-Z State
Parallel 16 Bits
Binary Twos Complement
+0.4
+4
±
5
15
83
83
V
V
µA
pF
ns
ns
4.75
4.75
5
5
3.0
11
5.25
5.25
100
–40
+85
V
V
mA
mA
mW
°C
TIMING SPECIFICATIONS
(AD976A: F = 200 kHz; AD976: F = 100 kHz; –40 C to +85 C, V
模拟电子
