Data Sheet
FEATURES
Dual 12-/14-/16-Bit 800 MSPS DAC
with Low Power 32-Bit Complex NCO
AD9785/AD9787/AD9788
GENERAL DESCRIPTION
The
AD9785/AD9787/AD9788
are 12-bit, 14-bit, and 16-bit,
high dynamic range TxDAC® devices, respectively, that provide
a sample rate of 800 MSPS, permitting multicarrier generation
up to the Nyquist frequency. Features are included for optimizing
direct conversion transmit applications, including complex
digital modulation, as well as gain, phase, and offset compens-
ation. The DAC outputs are optimized to interface seamlessly
with analog quadrature modulators, such as the
ADL5375
family from Analog Devices, Inc. A serial peripheral interface
(SPI) provides for programming and readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The
AD9785/AD9787/AD9788
family is manufactured on a 0.18 μm CMOS process and operates
from 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFP
package.
Analog output: adjustable 8.7 mA to 31.7 mA,
R
L
= 25 Ω to 50 Ω
Low power, fine complex NCO allows carrier placement
anywhere in DAC bandwidth while adding <300 mW power
Auxiliary DACs allow I and Q gain matching and offset control
Includes programmable I and Q phase compensation
Internal digital upconversion capability
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed pad TQFP package
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM
Digital high or low IF synthesis
Transmit diversity
Wideband communications
LMDS/MMDS, point-to-point
PRODUCT HIGHLIGHTS
1.
Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
Proprietary DAC output switching technique enhances
dynamic performance.
CMOS data input interface with adjustable setup and hold.
Low power complex 32-bit numerically controlled
oscillators (NCOs).
2.
3.
4.
TYPICAL SIGNAL CHAIN
COMPLEX I AND Q
DC
DC
DIGITAL INTERPOLATION FILTERS
I DAC
FPGA/ASIC/DSP
Q DAC
POST DAC
ANALOG FILTER
A
07098-001
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
LO
Figure 1.
Rev. C
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AD9785/AD9787/AD9788
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Serial Port Interface .................................................................... 21
SPI Register Map............................................................................. 24
SPI Register Descriptions .......................................................... 25
Input Data Ports .............................................................................. 33
Single-Port Mode........................................................................ 33
Dual-Port Mode .......................................................................... 33
Input Data Referenced to DATACLK ...................................... 33
Input Data Referenced to REFCLK.......................................... 35
Optimizing the Data Input Timing .......................................... 36
Data Sheet
Input Data RAM ......................................................................... 37
Digital Datapath ............................................................................. 38
Interpolation Filters ................................................................... 38
Quadrature Modulator .............................................................. 40
Numerically Controlled Oscillator .......................................... 40
Inverse Sinc Filter ....................................................................... 40
Digital Amplitude and Offset Control .................................... 41
Digital Phase Correction ........................................................... 41
Device Synchronization ................................................................. 42
Synchronization Logic Overview ............................................. 42
Synchronizing Devices to a System Clock .............................. 44
Synchronizing Multiple Devices to Each Other ..................... 45
Interrupt Request Operation .................................................... 46
Driving the REFCLK Input ........................................................... 47
DAC REFCLK Configuration ................................................... 47
Analog Outputs............................................................................... 50
Digital Amplitude Scaling ......................................................... 50
Power Dissipation ........................................................................... 52
AD9785/AD9787/AD9788 Evaluation Boards........................... 54
Output Configuration ................................................................ 54
Digital Picture of Evaluation Board ......................................... 54
Evaluation Board Software ........................................................ 55
Evaluation Board Schematics ................................................... 56
Outline Dimensions ....................................................................... 62
Ordering Guide .......................................................................... 62
REVISION HISTORY
5/2018—Rev. B to Rev. C
Change to Table 32 ......................................................................... 45
2/2016—Rev. A to Rev. B
Changed SPI_CSB to SPI_CS....................................... Throughout
Changes to General Description Section ...................................... 1
Changes to Figure 2 and Table 6 ..................................................... 7
Changes to Figure 3 and Table 7 ..................................................... 9
Changes to Figure 4 and Table 8 ................................................... 11
Changes to Figure 52 ...................................................................... 36
Updated Outline Dimensions ....................................................... 62
Changes to Ordering Guide .......................................................... 62
2/2009—Rev. 0 to Rev. A
Added Settling Time, to Within ±0.5 LSBs Parameter, Table 1...3
Added REFCLK Frequency Range, PLL Enabled Parameter,
Table 2 .................................................................................................4
Changes to SPI_SDIO—Serial Data I/O Section ....................... 23
Changes to Table 9.......................................................................... 24
Changes to Table 11 ....................................................................... 26
Changes to Table 12 ....................................................................... 27
Changes to Table 13 ....................................................................... 28
Changes to Table 22 ....................................................................... 32
Changes to Dual-Port Mode Section ........................................... 33
Changes to Input Data RAM Section .......................................... 37
Changes to Digital Amplitude and Offset Control Section ...... 41
Changes to Direct Clocking Section ............................................ 47
1/2008—Revision 0: Initial Version
Rev. C | Page 2 of 62
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD9785/AD9787/AD9788
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFS
= 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE 1596 reduced range link, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Guaranteed
Settling Time, to Within ±0.5 LSBs
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current
1
Output Compliance Range (Source)
Output Compliance Range (Sink)
Output Resistance
Aux DAC Monotonicity Guaranteed
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
POWER CONSUMPTION
1× Mode, f
DATA
= 100 MSPS,
PLL Off, IF = 2 MHz
2× Mode, f
DATA
= 100 MSPS,
Inverse Sinc Off, PLL Off
4× Mode, f
DATA
= 100 MSPS,
Inverse Sinc Off, PLL Off
8× Mode, f
DATA
= 100 MSPS,
Inverse Sinc Off, PLL Off
Power-Down Mode
OPERATING RANGE
1
Min
AD9785
Typ
Max
12
±0.2
±0.3
Min
AD9787
Typ
Max
14
±0.5
±1.0
Min
AD9788
Typ
Max
16
±2.1
±3.7
Unit
Bits
LSB
LSB
–0.001
8.66
–1.0
0
±2
20.2
10
10
20
0.04
100
30
10
+0.001
31.66
+1.0
−0.001
8.66
–1.0
0
±2
20.2
10
10
20
0.04
100
30
10
+0.001
31.66
+1.0
−0.001
8.66
–1.0
0
±2
20.2
10
10
20
0.04
100
30
10
+0.001
31.66
+1.0
% FSR
% FSR
mA
V
MΩ
Bits
ns
ppm/°C
ppm/°C
ppm/°C
Bits
mA
V
V
MΩ
Bits
V
kΩ
–1.998
0
0.8
1
10
1.2
5
3.13
1.70
3.13
1.70
3.3
1.8
3.3
1.8
375
533
754
1054
2.5
+25
+1.998
1.6
1.6
–1.998
0
0.8
1
10
1.2
5
+1.998
1.6
1.6
–1.998
0
0.8
1
10
1.2
5
+1.998
1.6
1.6
3.47
1.90
3.47
1.90
450
3.13
1.70
3.13
1.70
3.3
1.8
3.3
1.8
375
533
754
1054
3.47
1.90
3.47
1.90
450
3.13
1.70
3.13
1.70
3.3
1.8
3.3
1.8
375
533
754
1054
3.47
1.90
3.47
1.90
450
V
V
V
V
mW
mW
mW
mW
–40
9.0
+85
–40
2.5
+25
9.0
+85
–40
2.5
+25
9.0
+85
mW
°C
Based on a 10 Ω external resistor.
Rev. C | Page 3 of 62
AD9785/AD9787/AD9788
DIGITAL SPECIFICATIONS
Data Sheet
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFS
= 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input V
IN
Logic High
Input V
IN
Logic Low
LVDS INPUT (SYNC_I+, SYNC_I−)
Input Voltage Range, V
IA
or V
IB
Input Differential Threshold, V
IDTH
Input Differential Hysteresis, V
IDTHH
− V
IDTHL
Receiver Differential Input Impedance, R
IN
LVDS Input Rate (f
SYNC_I
= f
DATA
)
Setup Time, SYNC_I to DAC Clock
Hold Time, SYNC _I to DAC Clock
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
Output Voltage High, V
OA
or V
OB
Output Voltage Low, V
OA
or V
OB
Output Differential Voltage, |V
OD
|
Output Offset Voltage, V
OS
Output Impedance, Single-Ended, R
O
DAC CLOCK INPUT (REFCLK+, REFCLK–)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
REFCLK Frequency Range, PLL Enabled
MAXIMUM INPUT DATA RATE
1× Interpolation
2× Interpolation
4× Interpolation
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
8× Interpolation
DVDD18 = 1.8 V ±5%
DVDD18 = 1.9 V ± 5%
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time, SPI_SDIO to SCLK
Hold Time, SPI_SDIO to SCLK
Setup Time, SPI_CS to SCLK
Data Valid, SPI_SDO to SCLK
INPUT DATA
Setup Time, Input Data to DATACLK
Hold Time, Input Data to DATACLK
Setup Time, Input Data to REFCLK
Hold Time, Input Data to REFCLK
Test Conditions/Comments
Min
2.0
0.8
SYNC_I+ = V
1A
, SYNC_I− = V
1B
825
–100
20
80
30
0.45
0.25
SYNC_O+ = V
OA
, SYNC_O− = V
OB
, 100 Ω termination
825
1025
150
1150
80
400
300
800
900
30
250
250
200
225
100
112.5
40
12.5
12.5
2.8
0.0
3.0
10.0
All modes, −40°C to +85°C
1
460
−1.5
−0.25
2.4
ns
ns
ns
ns
1575
200
100
800
400
250
1250
120
1600
500
mV
mV
mV
mV
Ω
mV
mV
MHz
MHz
MHz
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MHz
ns
ns
ns
ns
ns
ns
120
1575
+100
mV
mV
mV
Ω
MHz
ns
ns
Typ
Max
Unit
V
V
250
Rev. C | Page 4 of 62
Data Sheet
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Inverse Sinc
POWER-UP TIME
2
DAC Wake-Up Time
3
DAC Sleep Time
4
1
2
AD9785/AD9787/AD9788
Test Conditions/Comments
With or without modulation
With or without modulation
With or without modulation
With or without modulation
Min
Typ
40
83
155
294
18
260
22
22
Max
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
ms
ms
ms
I
OUT
current settling to 1%
I
OUT
current to less than 1% of full scale
Timing vs. temperature and data valid windows are delineated in Table 25.
Measured from SPI_CS rising edge on Register 0x00; toggle Bit 4 from 0 to 1. VREF decoupling capacitor = 0.1 µF.
3
Measured from SPI_CS rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 0 to 1.
4
Measured from SPI_CS rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 1 to 0.
AC SPECIFICATIONS
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
OUTFS
= 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (IN-BAND SFDR)
f
DACCLK
= 200 MSPS, f
OUT
= 70 MHz 1× Interpolation
f
DACCLK
= 200 MSPS, f
OUT
= 70 MHz 2× Interpolation
f
DACCLK
= 200 MSPS, f
OUT
= 70 MHz 4× Interpolation
f
DACCLK
= 800 MSPS, f
OUT
= 40 MHz 8× Interpolation
TWO-TONE INTERMODULATION DISTORTION (IMD)
f
DATA
= 200 MSPS, f
OUT
= 50 MHz 1× Interpolation
f
DATA
= 200 MSPS, f
OUT
= 50 MHz 2× Interpolation
f
DATA
= 200 MSPS, f
OUT
= 100 MHz 4× Interpolation
f
DATA
= 100 MSPS, f
OUT
= 100 MHz 8× Interpolation
NOISE SPECTRAL DENSITY (NSD), EIGHT TONE, 500 kHz TONE
SPACING
f
DACCLK
= 200 MSPS, f
OUT
= 80 MHz
f
DACCLK
= 400 MSPS, f
OUT
= 80 MHz
f
DACCLK
= 800 MSPS, f
OUT
= 80 MHz
WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
f
DACCLK
= 491.52 MSPS, f
OUT
= 100 MHz 4× Interpolation
f
DACCLK
= 491.52 MSPS, f
OUT
= 200 MHz 4× Interpolation
WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO
(ACLR), SINGLE CARRIER
f
DACCLK
= 491.52 MSPS, f
OUT
= 100 MHz 4× Interpolation
f
DACCLK
= 491.52 MSPS, f
OUT
= 200 MHz 4× Interpolation
AD9785
Min Typ Max
80
80
78
85
80
78
78
70
AD9787
Min Typ Max
82
82
80
87
82
79
79
70
AD9788
Min Typ Max
83
83
81
90
83
80
80
70
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−154
−154
−154
−157
−158
−159
−158
−161
−162
dBm/Hz
dBm/Hz
dBm/Hz
78
72
80
74
82
76
dBc
dBc
80
78
82
80
88
82
dBc
dBc
Rev. C | Page 5 of 62
