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FEATURES

3 V/5 V Power Supply

25 MHz Speed

On-Chip SINE Look-Up Table

On-Chip 10-Bit DAC

Parallel Loading

Powerdown Option

72 dB SFDR

125 mW (5 V) Power Consumption

40 mW (3 V) Power Consumption

48-Pin

LQFP

APPLICATIONS

DDS Tuning

Digital Demodulation

DIRECT DIGITAL SYNTHESIZER,

WAVEFORM GENERATOR

AD9831

GENERAL DESCRIPTION

This DDS device is a numerically controlled oscillator employ-

ing a phase accumulator, a sine look-up table and a 10-bit D/A

converter integrated on a single CMOS chip. Modulation

capabilities are provided for phase modulation and frequency

modulation.

Clock rates up to 25 MHz are supported. Frequency accuracy

can be controlled to one part in 4 billion. Modulation is effected

by loading registers through the parallel microprocessor

interface.

A powerdown pin allows external control of a powerdown

mode. The part is available in a 48-pin

LQFP

package.

Similar DDS products can be found at

http://www.analog.com/DDS.

FUNCTIONAL BLOCK DIAGRAM

DVDD

DGND

AVDD

AGND

REFOUT

FS ADJUST

REFIN

MCLK

FSELECT

FREQ0 REG

MUX

FREQ1 REG

ON-BOARD

REFERENCE

FULL-SCALE

CONTROL

COMP

PHASE

ACCUMULATOR

(32-BIT)

SIN

ROM

10-BIT DAC

IOUT

PHASE0 REG

PHASE1 REG

PHASE2 REG

PHASE3 REG

MUX

AD9831

PARALLEL REGISTER

SLEEP

TRANSFER CONTROL

RESET

MPU INTERFACE

D15

PSEL0

PSEL1

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

2011

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:

781.329.4700

Fax:

781.461.3113

AD9831–SPECIFICATIONS

Parameter

SIGNAL DAC SPECIFICATIONS

Resolution

Update Rate (f

MAX

)

OUT

Full Scale

Output Compliance

DC Accuracy

Integral Nonlinearity

Differential Nonlinearity

DDS SPECIFICATIONS

Dynamic Specifications

Signal to Noise Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range (SFDR)

Narrow Band (± 50 kHz)

Wide Band (± 2 MHz)

Clock Feedthrough

Wake-Up Time

Powerdown Option

VOLTAGE REFERENCE

Internal Reference @ +25°C

MIN

to T

MAX

REFIN Input Impedance

Reference TC

REFOUT Output Impedance

LOGIC INPUTS

INH

, Input High Voltage

INL

, Input Low Voltage

INH

, Input Current

, Input Capacitance

POWER SUPPLIES

AVDD

DVDD

+ I

DD5

Low Power Sleep Mode

1.5

0.5

= +3.3 V

10%; +5 V 10%; AGND = DGND = 0 V; T

= T

MIN

to T

MAX

; REFIN =

REFOUT; R

SET

= 3.9 k ; R

LOAD

= 300 for IOUT unless otherwise noted)

Units

Bits

MSPS nom

mA nom

mA max

V max

LSB typ

Test Conditions/Comments

AD9831A

–53

–72

–70

–50

–60

Yes

1.21

100

300

– 0.9

0.9

2.97/5.5

2.5 + 0.33/MHz

dB min

dBc max

dBc min

dBc typ

ms typ

MCLK

= 25 MHz, f

OUT

= 1 MHz

MCLK

= 25 MHz, f

OUT

= 1 MHz

MCLK

= 6.25 MHz, f

OUT

= 2.11 MHz

5 V Power Supply

3 V Power Supply

Volts typ

Volts min/max

MΩ typ

ppm/°C typ

Ω

typ

V min

V max

µA

max

pF max

V min/V max

mA max

mA typ

mA max

5 V Power Supply

3 V Power Supply

5 V Power Supply

1 MΩ Resistor Tied Between REFOUT and AGND

NOTES

Operating temperature range is as follows: A Version: –40°C to +85°C.

100% production tested.

MCLK

= 6.25 MHz, Frequency Word = 5671C71C HEX, f

OUT

= 2.11 MHz.

See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.

Measured with the digital inputs static and equal to 0 V or DVDD.

The Low Power Sleep Mode current is typically 2 mA when a 1 M

Ω

resistor is not tied between REFOUT and AGND.

The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-

ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.

Specifications subject to change without notice.

SET

3.9kΩ

10nF

REFOUT

REFIN

ADJUST

COMP

AVDD

10nF

ON-BOARD

REFERENCE

FULL-SCALE

CONTROL

SIN

ROM

10-BIT DAC

IOUT

300Ω

50pF

AD9831

Figure 1. Test Circuit with Which Specifications Are Tested

–2–

REV. B

AD9831

TIMING CHARACTERISTICS

Parameter

Limit at

MIN

to T

MAX

(A Version)

= +3.3 V

10%, +5 V

10%; AGND = DGND = 0 V, unless otherwise noted)

Units

ns min

Test Conditions/Comments

MCLK Period

MCLK High Duration

MCLK Low Duration

Rising Edge to MCLK Rising Edge

Rising Edge After MCLK Rising Edge

Pulse Width

Duration between Consecutive

Pulses

Data/Address Setup Time

Data/Address Hold Time

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

RESET

Pulse Duration

*See Pin Description section.

Guaranteed by design but not production tested.

MCLK

Figure 2. Clock Synchronization Timing

A0, A1, A2

DATA

VALID DATA

Figure 3. Parallel Timing

MCLK

FSELECT

PSEL0, PSEL1

VALID DATA

RESET

Figure 4. Control Timing

REV. B

–3–

AD9831

ABSOLUTE MAXIMUM RATINGS*

= +25°C unless otherwise noted)

PIN CONFIGURATION

FS ADJUST

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C

LQFP

Thermal Impedance . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

COMP

REFIN

AGND

AVDD

IOUT

48 47 46 45 44 43 42 41 40 39 38 37

AGND

REFOUT

PIN 1

IDENTIFIER

AGND

RESET

DB0

DB1

DGND

DB2

DB3

DB4

DVDD

SLEEP

DVDD

DGND

MCLK

DVDD

FSELECT

PSEL0

PSEL1

13 14 15 16 17 18 19 20 21 22 23 24

AD9831

TOP VIEW

(Not to Scale)

DGND

DB15

DB14

DB13

DB12

DB10

NC = NO CONNECT

DB11

DB9

DB8

DB7

DB6

DB5

–4–

REV. B

AD9831

PIN DESCRIPTION

Mnemonic

Function

POWER SUPPLY

AVDD

Positive power supply for the analog section. A 0.1

µF

decoupling capacitor should be connected between AVDD

and AGND. AVDD can have a value of +5 V

10% or +3.3 V

10%.

AGND

Analog Ground.

DVDD

Positive power supply for the digital section. A 0.1

µF

decoupling capacitor should be connected between DVDD

and DGND. DVDD can have a value of +5 V

10% or +3.3 V

10%.

DGND

Digital Ground.

ANALOG SIGNAL AND REFERENCE

IOUT

Current Output. This is a high impedance current source. A load resistor should be connected between IOUT

and AGND.

FS ADJUST

Full-Scale Adjust Control. A resistor (R

SET

) is connected between this pin and AGND. This determines the

magnitude of the full-scale DAC current. The relationship between R

SET

and the full-scale current is as follows:

IOUT

FULL-SCALE

= 12.5

REFIN

SET

REFIN

= 1.21

V nominal, R

SET

= 3.9 kΩ

typical

REFIN

Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin

REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831

accepts a reference of 1.21 V nominal.

REFOUT

Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is

made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT

to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.

COMP

Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic

capacitor should be connected between COMP and AVDD.

DIGITAL INTERFACE AND CONTROL

MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The

output frequency accuracy and phase noise are determined by this clock.

FSELECT

Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase

accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an

MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one

MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change

on FSELECT should not coincide with an MCLK rising edge.

Write, Edge-Triggered Digital Input. The

pin is used when writing data to the AD9831. The data is loaded

into the AD9831 on the rising edge of the

pulse. This data is then loaded into the destination register on the

MCLK rising edge. The

pulse rising edge should not coincide with the MCLK rising edge as there will be an

uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The

rising

edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the

MCLK rising edge. Alternatively, the

rising edge can occur after the MCLK rising edge and the destination

D0–D15

Data Bus, Digital Inputs for destination registers.

A0–A2

Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to

be written.

PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being

input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the

inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1

are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising

edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase

SLEEP

Low Power Control, active low digital input.

SLEEP

puts the AD9831 into a low power mode. Internal clocks

are disabled and the DAC’s current sources and REFOUT are turned off. The AD9831 is re-enabled by taking

SLEEP

high.

RESET

Reset, active low digital input.

RESET

resets the phase accumulator to zero which corresponds to an analog

output of midscale.

REV. B

–5–