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o e n oe p ae it w . e c o
a
e
s
o ec
a
Mixed-Signal Front-End (MxFE
™
) Processor
for Broadband Communications
AD9860/AD9862
*
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
1x
PGA
ADC
BYPASSABLE LOW-PASS
DECIMATION FILTER
VIN+B
VIN–B
SIGDELT
1x
PGA
ADC
RxB DATA
[0:11]
HILBERT
FILTER
RxA DATA
[0:11]
FEATURES
Mixed-Signal Front-End Processor with Dual Converter
Receive and Dual Converter Transmit Signal Paths
Receive Signal Path Includes:
Two 10-/12-Bit, 64 MSPS Sampling A/D Converters
with Internal or External Independent References,
Input Buffers, Programmable Gain Amplifiers,
Low-Pass Decimation Filters, and a Digital Hilbert Filter
Transmit Signal Path Includes:
Two 12-/14-Bit, 128 MSPS D/A Converters with
Programmable Full-Scale Output Current, Channel
Independent Fine Gain and Offset Control, Digital
Hilbert and Interpolation Filters, and Digitally Tunable
Real or Complex Up-Converters
Delay-Locked Loop Clock Multiplier and Integrated
Timing Generation Circuitry Allow for Single Crystal
or Clock Operation
Programmable Output Clocks, Serial Programmable
Interface, Programmable Sigma-Delta, Three Auxiliary
DAC Outputs and Two Auxiliary ADCs with Dual
Multiplexed Inputs
APPLICATIONS
Broadband Wireless Systems
Fixed Wireless, WLAN, MMDS, LMDS
Broadband Wireline Systems
Cable Modems, VDSL, PowerPlug
Digital Communications
Set-Top Boxes, Data Modems
GENERAL DESCRIPTION
-
LOGIC LOW
AD9860/AD9862
SPI REGISTERS
SPI
INTERFACE
AUX_DAC_A
AUX_DAC_B
AUX_DAC_C
AUX DAC
AUX DAC
AUX DAC
Rx PATH
TIMING
Tx PATH
TIMING
AUX ADC
CLOCK
DISTRIBUTION
BLOCK
DLL
1 ,2 ,4
OSC1
OSC2
AUX_ADC_A1
AUX_ADC_A2
AUX_ADC_B1
AUX ADC
AUX_ADC_B2
CLKOUT1
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
CLKOUT2
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
IOUT+A
IOUT–A
IOUT+B
IOUT–B
PGA
DAC
FS/4
FS/8
PGA
DAC
HILBERT
FILTER
Tx DATA
[0:13]
BYPASSABLE
LOW-PASS
INTERPOLATION
FILTER
NCO
range for both channels. The output data bus can be multi-
plexed to accommodate a variety of interface types.
The AD9860/AD9862 transmit path (Tx) consists of two chan-
nels that contain high performance, 12-/14-bit, 128 MSPS
digital-to-analog converters (DAC), programmable gain amplifiers
(TxPGA), interpolation filters, a Hilbert filter, and digital mixers
for complex or real signal frequency modulation. The Tx latch
and demultiplexer circuitry can process real or I/Q data. Interpo-
lation rates of 2 and 4 are available to ease requirements on
an external reconstruction filter. For single channel systems, the
digital Hilbert filter can be used with an external quadrature
modulator to create an image rejection architecture. The two
12-/14-bit, high performance DACs produce an output signal
that can be scaled over a 20 dB range by the TxPGA.
A programmable delay-locked loop (DLL) clock multiplier and
integrated timing circuits enable the use of a single external
reference clock or an external crystal to generate clocking for all
internal blocks and also provides two external clock outputs.
Additional features include a programmable sigma-delta output,
four auxiliary ADC inputs and three auxiliary DAC outputs.
Device programmability is facilitated by a serial port interface
(SPI) combined with a register bank. The AD9860/AD9862 is
available in a space saving 128-lead LQFP.
The AD9860 and AD9862 (AD9860/AD9862) are versatile
integrated mixed-signal front-ends (MxFE) that are optimized
for broadband communication markets. The AD9860/AD9862
are cost effective, mixed signal solutions for wireless or wireline
standards based or proprietary broadband modem systems where
dynamic performance, power dissipation, cost, and size are all
critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;
the AD9862 has 12-bit ADCs and 14-bit DACs.
The AD9860/AD9862 receive path (Rx) consists of two channels
that each include a high performance, 10-/12-bit, 64 MSPS analog-
to-digital converter (ADC), input buffer, Programmable Gain
Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The
Rx can be used to receive real, diversity, or I/Q data at baseband or
low IF. The input buffers provide a constant input impedance for
both channels to ease impedance matching with external com-
ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain
*Protected
by U.S.Patent No.
5,969,657.
MxFE is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9860/AD9862–SPECIFICATIONS
Tx PARAMETERS
12-/14-BIT DAC CHARACTERISTICS
Resolution
Maximum Update Rate
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Negative Differential Nonlinearity (–DNL)
Positive Differential Nonlinearity (+DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 6 MHz Tone
Crystal and OSC IN Multiplier Enabled at 4
Output Voltage Compliance Range
TRANSMIT TxPGA CHARACTERISTICS
Gain Range
Step Size Accuracy
Step Size
Tx DIGITAL FILTER CHARACTERISTICS
Hilbert Filter Pass Band (<0.1 dB Ripple)
2 /4 Interpolator Stop Band
2
DYNAMIC PERFORMANCE (A
OUT
= 20 mA FS, f = 1 MHz)
Differential Phase
Differential Gain
AD9860 Signal-to-Noise Ratio (SNR)
AD9860 Signal-to-Noise and Distortion Ratio
AD9860 Total Harmonic Distortion (THD)
AD9860 Wideband SFDR (to Nyquist)
1 MHz Analog Out, I
OUT
= 2 mA
1 MHz Analog Out, I
OUT
= 20 mA
6 MHz Analog Out, I
OUT
= 20 mA
AD9860 Narrowband SFDR (1 MHz Window)
1 MHz Analog Out, I
OUT
= 2 mA
1 MHz Analog Out, I
OUT
= 20 mA
AD9862 Signal-to-Noise Ratio (SNR)
AD9862 Signal-to-Noise and Distortion Ratio
AD9862 Total Harmonic Distortion (THD)
AD9862 Wideband SFDR (to Nyquist)
1 MHz Analog Out, I
OUT
= 2 mA
1 MHz Analog Out, I
OUT
= 20 mA
6 MHz Analog Out, I
OUT
= 20 mA
AD9862 Narrowband SFDR (1 MHz Window)
1 MHz Analog Out, I
OUT
= 2 mA
1 MHz Analog Out, I
OUT
= 20 mA
Rx PARAMETERS
RECEIVE BUFFER
Input Resistance (Differential)
Input Capacitance (Each Input)
Maximum Input Bandwidth (–3 dB)
Analog Input Range (Best Noise Performance)
Analog Input Range (Best THD Performance)
RECEIVE PGA CHARACTERISTICS
Gain Error
Gain Range
Step Size Accuracy
Step Size
Input Bandwidth (–3 dB, Rx Buffer Bypassed)
10-/12-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Full
Full
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
NA
Full
Temp
NA
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Full
25ºC
25ºC
25ºC
Full
Full
25ºC
25ºC
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
(V
A
= 3.3 V 5%, V
D
= 3.3 V 10%, f
DAC
= 128 MHz, f
ADC
= 64 MHz
Normal Timing Mode, 2 DLL Setting, R
SET
= 4 k , 50 DAC Load,
RxPGA = +6 dB Gain, TxPGA = +20 dB Gain.)
Test
Level
NA
I
I
I
I
III
III
III
III
III
II
III
III
III
II
II
III
III
I
I
I
III
I
III
III
I
I
I
I
III
I
III
III
I
12.5
128
2
–5.5
–1
1.15
Min
AD9860/AD9862
Typ
12/14
20
+5.5
+1
1.28
Max
Unit
Bits
MSPS
mA
%FS
%FS
V
LSB
LSB
LSB
pF
dBc/Hz
V
dB
dB
dB
38
±
38
<0.1
<1
70.7
66.1
–74.5
70.6
75
75
70.2
90
72.0
69.8
–75.5
70.6
76.0
76.0
70.2
90
% f
DATA1
% f
DATA
Degree
LSB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
+0.5
0.0
1.22
–0.5/–0.5
1/2
±
1/± 3
5
–115
–0.5
20
±
0.1
0.08
+1.5
68.2
62.5
–64.0
64.4
83
68.9
64.75
–65.0
64.9
83
III
III
III
II
II
I
I
I
I
III
NA
I
200
5
140
2
1
±
0.3
20
±
0.2
1
250
10/12
64
W
pF
MHz
V p-p Diff
V p-p Diff
dB
dB
dB
dB
MHz
Bits
19
21
MHz
REV. 0
–2–
AD9860/AD9862
Rx PARAMETERS (continued)
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Offset Error
Gain Error
Aperture Delay
Aperture Uncertainty (Jitter)
Input Referred Noise
Reference Voltage Error
REFT-REFB Error (1 V)
Temp
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Test
Level
III
III
III
III
III
III
III
I
I
I
I
I
I
I
I
I
III
III
59.0
56.0
70.3
62.6
62.5
77.09
Min
AD9860/AD9862
Typ
Max
±
0.3/± 0.4
±
1.2/± 5
±
0.1
±
0.2
2.0
1.2
250
±
1
60.66
58.0
–76.5
81.0
64.2
64.14
–79.22
85.13
>90
>80
±
4
Unit
LSB
LSB
%FSR
%FSR
ns
ps rms
µV
mV
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
AD9860 DYNAMIC PERFORMANCE (A
IN
= –0.5 dBFS, f = 5 MHz)
Signal-to-Noise Ratio
25∞C
Signal-to-Noise and Distortion Ratio
25∞C
Total Harmonic Distortion
25∞C
Spurious Free Dynamic Range
25∞C
AD9862 DYNAMIC PERFORMANCE (A
IN
= –0.5 dBFS, f = 5 MHz)
Signal-to-Noise Ratio
25∞C
Signal-to-Noise and Distortion Ratio
25∞C
Total Harmonic Distortion
25∞C
Spurious Free Dynamic Range
25∞C
CHANNEL-TO-CHANNEL ISOLATION
Tx-to-Rx (A
OUT
= 0 dBFS, f
OUT
= 7 MHz)
Rx Channel Crosstalk (f
1
= 6 MHz, f
2
= 9 MHz)
PARAMETERS
CMOS LOGIC INPUTS
Logic “1” Voltage, V
IH
Logic “0” Voltage, V
IL
Logic “1” Current
Logic “0” Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage, V
OH
Logic “0” Voltage, V
OL
POWER SUPPLY
Analog Supply Currents
Tx (Both Channels, 20 mA FS Output)
Tx Powered Down
Rx (Both Channels, Input Buffer Enabled)
Rx (Both Channels, Input Buffer Disabled)
Rx (32 MSPS, Low Power Mode, Buffer Disabled)
Rx (16 MSPS, Low Power Mode, Buffer Disabled)
Rx Path Powered Down
DLL
Digital Supply Current
AD9860 Both Rx and Tx Path (All Channels Enabled)
2 Interpolation, f
DAC
= f
ADC
= 64 MSPS
AD9862 Both Rx and Tx Path (All Channels Enabled)
2 Interpolation, f
DAC
= f
ADC
= 64 MSPS
Tx Path (f
DAC
= 128 MSPS)
Processing Blocks Disabled
4 Interpolation
4 Interpolation, Coarse Modulation
4 Interpolation, Fine Modulation
4 Interpolation, Coarse and Fine Modulation
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
–70.5
–73.2
II
II
II
II
III
II
II
DRVDD – 0.7
0.4
12
12
3
DRVDD – 0.6
0.4
V
V
µA
µA
pF
V
V
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
I
I
I
III
III
III
I
III
70
2.5
275
245
155
80
5.0
12
76
5.0
307
6.0
mA
mA
mA
mA
mA
mA
mA
mA
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
I
I
III
III
III
III
III
92
104
45
90
110
110
130
112
124
mA
mA
mA
mA
mA
mA
mA
REV. 0
–3–
AD9860/AD9862
PARAMETERS (continued)
POWER SUPPLY (continued)
Rx Path (f
ADC
= 64 MSPS)
Processing Blocks Disabled
Decimation Filter Enabled
Hilbert Filter Enabled
Hilbert and Decimation Filter Enabled
Temp
Test
Level
Min
AD9860/AD9862
Typ
Max
Unit
25ºC
25ºC
25ºC
25ºC
III
III
III
III
9
15
16
18.5
mA
mA
mA
mA
NOTES
1
% f
DATA
refers to the input data rate of the digital block.
2
Interpolation filter stop band is defined by image suppression of 50 dB or greater.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(20 pF Load)
Minimum Reset Pulsewidth Low (t
RL
)
Digital Output Rise/Fall Time
DLL Output Clock
DLL Output Duty Cycle
Tx–/Rx–Interface (See Figures 11 and 12)
TxSYNC/TxIQ Setup Time (t
Tx1
, t
Tx3
)
TxSYNC/TxIQ Hold Time (t
Tx2
, t
Tx4
)
RxSYNC/RxIQ/IF to Valid Time(t
Rx1
, t
Rx3
)
RxSYNC/RxIQ/IF Hold Time (t
Rx2
, t
Rx4
)
Serial Control Bus (See Figures 1 and 2)
Maximum SCLK Frequency (f
SCLK
)
Minimum Clock Pulsewidth High (t
HI
)
Minimum Clock Pulsewidth Low (t
LOW
)
Maximum Clock Rise/Fall Time
Minimum Data/SEN Setup Time (t
S
)
Minimum SEN/Data Hold Time (t
H
)
Minimum Data/SCLK Setup Time (t
DS
)
Minimum Data Hold Time (t
DH
)
Output Data Valid/SCLK Time (t
DV
)
AUXILARY ADC
Conversion Rate
Input Range
Resolution
AUXILARY DAC
Settling Time
Output Range
Resolution
ADC TIMING
Latency (All Digital Processing Blocks Disabled)
DAC Timing
Latency (All Digital Processing Blocks Disabled)
Latency (2 Interpolation Enabled)
Latency (4 Interpolation Enabled)
Additional Latency (Hilbert Filter Enabled)
Additional Latency (Coarse Modulation Enabled)
Additional Latency (Fine Modulation Enabled)
Output Settling Time (TST) (to 0.1%)
Specifications subject to change without notice.
Temp
NA
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Full
Full
Full
Full
Full
Full
Full
Full
Full
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
25ºC
Test
Level
NA
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
Min
5
2.8
32
AD9860/AD9862
Typ
Max
4
128
50
Unit
Clock Cycles
ns
MHz
%
ns
ns
ns
ns
MHz
ns
ns
ms
ns
ns
ns
ns
ns
MHz
V
Bits
ms
V
Bits
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ns
3
3
5.2
0.2
16
30
30
1
25
0
25
0
30
1.25
3
10
8
3
8
7
3
30
72
36
5
8
35
–4–
REV. 0
