a
A
FEATURES
Low Cost 3.3 V CMOS Mixed-Signal Front End (MxFE™)
Converter for Broadband Modems
10-/12-Bit D/A Converter (TxDAC+
®
)
64/32 MSPS Input Word Rate
2 /4 Interpolating LPF or BPF Transmit Filter
128 MSPS DAC Output Update Rate
Wide (26 MHz) Transmit Bandwidth
Power-Down Mode
10-/12-Bit 50 MSPS A/D Converter
Fourth Order Low-Pass Filter 12 MHz or 26 MHz
with Bypass
–6 dB to +36 dB Programmable Gain Amplifier
Internal Clock Multiplier (PLL)
Clock Outputs
Voltage Regulator Controller
48-Lead LQFP Package
APPLICATIONS
Powerline Networking
Home Phone Networking
xDSL
Broadband Wireless
Home RF
PRODUCT DESCRIPTION
PWR DN
Tx QUIET
GAIN
Tx [5:0]
Tx SYNC
Broadband Modem
Mixed-Signal Front End
AD9876
FUNCTIONAL BLOCK DIAGRAM
AD9876
Tx
MUX
12
Kx INTERPOLATION
LPF/BPF
12
TxDAC+
Tx+
Tx–
PLL-A
L
CLK-A
CLOCK GEN
CLK-B
Rx SYNC
PLL-B
M/N
V
REF
VRC
GATE
FB
OSCIN
XTAL
Rx [5:0]
Rx
MUX
12
ADC
PGA
LPF
PGA
Rx+
Rx–
SPORT
3
REGISTER
CONTROL
The AD9876 is a single-supply broadband modem mixed-signal
front end (MxFE) IC. The device contains a transmit path
interpolation filter and DAC and a receive path PGA, LPF, and
ADC supporting a variety of broadband modem applications.
Also on-chip is a PLL clock multiplier that provides all required
clocks from a single crystal or clock input. The AD9876 provides
12-bit converter performance on both the Tx and Rx path.
The TxDAC+ uses a selectable digital 2× or 4× interpolation
low-pass or band-pass filter to further oversample transmit data
and reduce the complexity of analog reconstruction filtering.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64 MSPS. The 12-bit DAC provides
differential current outputs for optimum noise and distortion
performance. The DAC full-scale current can be adjusted from
2 to 20 mA by a single resistor, providing 20 dB of additional
gain range.
The receive path consists of a PGA, LPF, and ADC. The PGA has
a gain range of –6 dB to +36 dB, programmable in 2 dB steps,
adding 42 dB of dynamic range to the receive path. The receive
path LPF cutoff frequency can be programmed to either 12 MHz
or 26 MHz. The filter cutoff frequency can also be tuned or
bypassed where filter requirements differ. The 12-bit ADC uses
a multistage differential pipeline architecture to achieve excellent
dynamic performance with low power consumption.
The AD9876 provides a voltage regulator controller (VRC) that
can be used with an external power MOSFET transistor to form
a cost-effective 1.3 V linear regulator.
The digital transmit and receive ports are each multiplexed to a
bus width of six bits and are clocked at a frequency of twice the
12-bit word rate.
The AD9876 ADC and/or DAC can also be used at sampling
rates as high as 64 MSPS in a 6-bit resolution nonmulti-
plexed mode.
The AD9876 is pin compatible with the 10-bit AD9875. Both are
available in a space-saving 48-lead LQFP package. They are speci-
fied over the industrial (–40°C to +85°C) temperature range.
MxFE is a trademark of Analog Devices, Inc.
TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
2
781/326-8703
Fax:
© Analog Devices, Inc., 2002
AD9876–SPECIFICATIONS
Parameter
OSCIN CHARACTERISTICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
CLOCK OUTPUT CHARACTERISTICS
CLK A Jitter (f
CLKA
Derived from PLL)
CLK A Duty Cycle
CLK B Jitter (f
CLKB
Derived from PLL)
CLK B Duty Cycle
Tx CHARACTERISTICS
Tx Path Latency, 4× Interpolation
Interpolation Filter Bandwidth (–0.1 dB)
4× Interpolation, LPF
2× Interpolation, LPF
TxDAC
Resolution
Conversion Rate
Full-Scale Output Current
Voltage Compliance Range
Gain Error
Output Offset (Single-Ended)
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
10 MHz Analog Out AD9876 (20 MHz BW)
Wideband SFDR (to Nyquist, 64 MHz Max)
5 MHz Analog Out
10 MHz Analog Out
Narrow-Band SFDR (3 MHz Window):
10 MHz Analog Out
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz)
Rx PATH CHARACTERISTICS
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
DC Accuracy
Differential Nonlinearity
Integral Nonlinearity
Dynamic Performance (ADC Clocked Direct)
(A
IN
= –0.5 dBFS, f = 5 MHz)
@ f
OSCIN
= 32 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Dynamic Performance (ADC Clocked, PLLB/2)
(A
IN
= –0.5 dBFS, f = 5 MHz)
@ F
PLLB/2
= 50 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
(V
S
= 3.3 V 10%, f
OSCIN
= 32 MHz, f
DAC
= 128 MHz, Gain = –6 dB, R
SET
= 4.02 k ,
100 DAC single-ended load, unless otherwise noted. )
Test
Level
II
II
III
III
III
III
III
III
II
II
II
II
II
II
II
II
II
III
III
III
III
I
III
III
III
III
III
NA
II
NA
II
II
Temp
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
NA
Full
NA
Full
Full
Min
10
40
Typ
Max
64
60
Unit
MHz
%
pF
M
ps rms
%
ps rms
%
f
DAC
Cycles
MHz
MHz
Bits
MHz
mA
V
% FS
µA
LSB
LSB
pF
dBc/Hz
dB
dBc
dBc
dBc
dBFS
Bits
MHz
Cycles
LSB
LSB
50
3
100
14
50
±
5
33
50
±
5
86
13
26
12
10
2
–0.5
–5
0
10
±
2
2
±
1
±
2
5
–100
65
80
74
88
–80
12
128
20
+1.5
+5
5
62.5
7.5
5.5
–1.0
–4.5
±
0.25
±
0.5
64
+1.0
+3.5
Full
Full
25°C
25°C
25°C
I
I
III
III
III
60.8
9.8
63.2
10.2
64
–70
72
dB
Bits
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
–2–
56
9.3
59
–63
68
dB
Bits
dB
dB
dB
REV. A
AD9876
Parameter
Rx PATH GAIN/OFFSET
Minimum Programmable Gain
Maximum Programmable Gain (12 MHz Filter)
Maximum Programmable Gain (26 MHz Filter)
Gain Step Size
Gain Step Accuracy
Gain Range Error
Offset Error, PGA Gain = 0 dB
Absolute Gain Error
Rx PATH INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Differential Input Resistance
Input Bandwidth (–3 dB)
Input Referred Noise (at –36 dB Gain with Filter)
Input Referred Noise (at –6 dB Gain with Filter)
Common-Mode Rejection
Rx PATH LPF (Low Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 22 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Rx PATH LPF (High Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 44 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Rx PATH DIGITAL HPF
Latency (ADC Clock Source Cycles)
Roll-Off in Stop Band
–3 dB Frequency
Rx PATH DISTORTION PERFORMANCE
IMD: f1 = 6.5 MHz, f2 = 7.7 MHz
12 MHz Filter : 0 dB Gain
: 30 dB Gain
26 MHz Filter : 0 dB Gain
: 30 dB Gain
POWER-DOWN/DISABLE TIMING
DAC I
OUT
OFF after Tx QUIET Asserted
DAC I
OUT
ON after Tx QUIET De-Asserted
Power-Down Delay (Active to Power-Down)
DAC
Interpolator
Power-Up Delay (Power-Down to Active)
DAC
PLL
ADC
PGA
LPF
Interpolator
VRC
Minimum RESET Pulsewidth Low (t
RL
)
REV. A
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Test
Level
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
II
II
II
Min
Typ
–6
36
30
2
±
0.4
±
1.0
±
10
±
0.8
4
4
270
50
16
684
40
12
±
7
20
±
1.0
30
150
–68
26
±
7
20
±
1.2
15
80
–65
1
6
f
ADC
/400
Max
Unit
dB
dB
dB
dB
dB
dB
LSB
dB
Vppd
pF
Ω
MHz
µV
rms
µV
rms
dB
MHz
%
dB
dB
ns
ns
dBc
MHz
%
dB
dB
ns
ns
dBc
Cycle
dB/Octave
Hz
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
III
III
III
III
II
II
II
II
II
II
II
II
II
II
II
II
–3–
–65
–57
–65
–56
200
1
400
200
40
10
1000
1
1
200
2
5
dBc
dBc
dBc
dBc
ns
µs
ns
ns
µs
µs
µs
µs
µs
ns
µs
f
OSCIN
Cycles
AD9876
Parameter
Tx PATH INTERFACE
Maximum Input Nibble Rate, 2× Interpolation
Tx Setup Time (t
SU
)
Tx Hold Time (t
HD
)
Rx PATH INTERFACE
Maximum Output Nibble Rate
Rx Data Valid Time (t
VT
)
Rx Data Hold Time (t
HT
)
SERIAL CONTROL BUS
Maximum SCLK Frequency (f
SCLK
)
Clock Pulsewidth High (t
PWH
)
Clock Pulsewidth Low (t
PWL
)
Clock Rise/Fall Time
Data/Chip-Select Setup Time (t
DS
)
Data Hold Time (t
DH
)
Data Valid Time (t
DV
)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage
Logic “0” Voltage
Digital Output Rise/Fall Time
POWER SUPPLY
All Blocks Powered Up
I
S_TOTAL
(Total Supply Current)
I
S_TOTAL
(Tx
QUIET
Pin Asserted)
Digital Supply Current (I
DRVDD
+ I
DVDD
)
Analog Supply Current (I
AVDD
)
Power Consumption of Functional Blocks:
Rx LPF
ADC and SPGA
Rx Reference
Interpolator
DAC
PLL-B
PLL-A
Voltage Regulator Controller
All Blocks Powered Down
Supply Current I
S
, f
OSCIN
= 32 MHz
Supply Current I
S
, f
OSCIN
Idle
Power Supply Rejection
Tx Path (∆V
S
= 10%)
Rx Path (∆V
S
= 10%)
RECEIVE-TO-TRANSMIT ISOLATION
(10 MHz, Full-Scale Sine Wave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB
VOLTAGE REGULATOR CONTROLLER
Output Voltage (V
FB
with SI2301 Connected)
Line Regulation (∆V
FB%
/∆V
DVDD%
×
100%)
Load Regulation (∆V
FB
/∆I
LOAD
)
Maximum Load Current (I
LOAD
)
Specifications subject to change without notice.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Test
Level
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
III
II
II
II
Min
128
3.0
0
110
Typ
Max
Unit
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
ms
ns
ns
ns
V
V
µA
µA
µF
V
V
ns
3.0
1.5
25
18
18
1
25
0
20
V
DRVDD
– 0.7
0.4
12
12
3
V
DRVDD
– 0.6
1.5
0.4
2.5
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
I
III
III
III
III
III
III
III
III
III
III
III
II
II
III
III
262
172
77
185
110
55
2
33
18
8
24
1
19
10
62
54
288
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
22
12
mA
mA
dB
dB
25°C
25°C
Full
25°C
25°C
Full
III
III
I
III
III
II
1.25
250
–75
–70
1.30
100
60
1.35
dB
dB
V
%
mΩ
mA
–4–
REV. A
AD9876
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Power Supply (V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
*Stresses
greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
I – Devices are 100% production tested at 25°C and guaran-
teed by design and characterization testing for industrial
operating temperature range (–40°C to +85°C).
II – Parameter is guaranteed by design and/or characteriza-
tion testing.
III – Parameter is a typical value only.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
JA
= 57°C/W
JC
= 28°C/W
ORDERING GUIDE
Model
AD9876BST
AD9876-EB
AD9876BSTRL
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead LQFP
Evaluation Board
BST Reel
Package Option
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9876 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–5–
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