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FEATURES
140 MSPS Maximum Conversion Rate
500 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
400 ps p-p PLL Clock Jitter
Power-Down Mode
3.3 V Power Supply
2.5 V to 3.3 V Three-State CMOS Outputs
Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 570 mW Typical
Internal PLL Generates CLOCK from HSYNC
Serial Port Interface
Fully Programmable
Supports Alternate Pixel Sampling for Higher-
Resolution Applications
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
GENERAL DESCRIPTION
R
IN
100 MSPS/140 MSPS
Analog Flat Panel Interface
AD9884A
FUNCTIONAL BLOCK DIAGRAM
AD9884A
8
CLAMP
8
A/D
8
R
OUTA
R
OUTB
G
OUTA
G
OUTB
B
OUTA
B
OUTB
DATACK
HSOUT
0.15V
CONTROL
8
G
IN
CLAMP
A/D
8
8
8
B
IN
CLAMP
A/D
2
CLOCK
GENERATOR
REF
8
8
HSYNC
COAST
CLAMP
CKINV
CKEXT
REFIN
FILT SOGIN SOGOUT SDA SCL A
0
A
1
PWRDN
REFOUT
The AD9884A is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports display resolutions of up to 1280
×
1024 (SXGA) at
75 Hz with sufficient input bandwidth to accurately acquire and
digitize each pixel.
To minimize system cost and power dissipation, the AD9884A
includes an internal 1.25 V reference, PLL to generate a pixel
clock from HSYNC, and programmable gain, offset and clamp
circuits. The user provides only a 3.3 V power supply, analog
input, and HSYNC signals. Three-state CMOS outputs may be
powered by a supply between 2.5 V and 3.3 V.
The AD9884A’s on-chip PLL generates a pixel clock from the
HSYNC input. Pixel clock output frequencies range from
20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p
relative to the input reference. When the COAST signal is pre-
sented, the PLL maintains its output frequency in the absence
of HSYNC. A 32-step sampling phase adjustment is provided.
Data, HSYNC and Data Clock output phase relationships are
always maintained. The PLL can be disabled and an external
clock input provided as the pixel clock.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a two-wire serial port.
Fabricated in an advanced CMOS process, the AD9884A is
provided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over a 0°C to +70°C temperature range.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9884A–SPECIFICATIONS
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew, t
SKEW
t
BUFF
t
STAH
t
DHO
t
DAL
t
DAH
t
DSU
t
STASU
t
STOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Current, High (I
IH
)
Input Current, Low (I
IL
)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (V
OH
)
Output Voltage, Low (V
OL
)
Duty Cycle
DATACK,
DATACK
Output Coding
25°C
Full
25°C
Full
Full
I
VI
I
VI
VI
Temp
Test
Level
(V
D
= 3.3 V, V
DD
= 3.3 V, PV
D
= 3.3 V, ADC Clock Frequency = Maximum, PLL
Clock Frequency = Maximum, Control Registers Programmed to Default State)
AD9884AKS-100
Min
Typ
Max
8
±
0.5
±
0.5
Guaranteed
±
1.0
±
1.0
±
1.25
±
1.75
AD9884AKS-140
Min
Typ
Max
8
±
0.5
±
0.8
Guaranteed
+1.15/–1.0
+1.25/–1.0
±
1.4
±
2.5
Unit
Bits
LSB
LSB
LSB
LSB
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
VI
VI
V
I
VI
VI
VI
VI
VI
V
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
VI
VI
VI
VI
V
VI
VI
IV
0.5
1.0
100
1
1
50
5.0
25
1.30
1.0
280
0.5
22
1.20
7
1.5
23.5
1.25
±
50
22
1.20
7
1.5
23.5
1.25
±
50
1
1
50
5.0
25
1.30
V p-p
V p-p
ppm/°C
µA
µA
mV
%FS
%FS
V
ppm/°C
MSPS
MSPS
ns
µs
µs
µs
µs
µs
ns
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
µA
µA
pF
V
V
%
100
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
100
400
15
2.5
0.8
–1.0
+1.0
3
V
DD
– 0.1
0.1
45
50
Binary
55
10
+2.0
140
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
140
475
15
2.5
0.8
–1.0
+1.0
3
V
DD
– 0.1
0.1
45
50
Binary
55
10
+2.0
110
20
700
1
1000
1
110
20
750
2
1000
2
–2–
REV. C
AD9884A
Parameter
POWER SUPPLY
V
D
Supply Voltage
V
DD
Supply Voltage
PV
D
Supply Voltage
I
D
Supply Current (V
D
)
I
DD
Supply Current (V
DD
)
3
IPV
D
Supply Current (PV
D
)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
4
(Without Harmonics)
f
IN
= 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θ
JC
–Junction-to-Case
Thermal Resistance
θ
JA
–Junction-to-Ambient
Thermal Resistance
Temp
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Test
Level
IV
IV
IV
V
V
V
VI
VI
VI
V
V
V
I
V
V
AD9884AKS-100
Min
Typ
Max
3.0
2.2
3.0
3.3
3.3
3.3
125
33
15
570
2.0
6.6
500
2
1.5
46.5
46.0
60
3.6
3.6
3.6
AD9884AKS-140
Min
Typ
Max
3.0
2.2
3.0
3.3
3.3
3.3
135
47
15
650
2.0
6.6
500
2
1.5
46.2
45.0
60
3.6
3.6
3.6
Unit
V
V
V
mA
mA
mA
mW
mA
mW
MHz
ns
ns
dB
dB
dBc
675
25
82.5
775
25
82.5
44.0
43.5
V
V
8.4
35
8.4
35
°C/W
°C/W
NOTES
1
VCORNGE = 01, CURRENT = 001, PLLDIV = 1693
10
.
2
VCORNGE = 10, CURRENT = 110, PLLDIV = 1600
10
.
3
DEMUX = 1; DATACK and
DATACK
load = 15 pF; Data load = 5 pF.
4
Using external pixel clock.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS
*
Model
Temperature Package
Range
Description
Package
Option
AD9884AKS-140 0°C to 70°C
AD9884AKS-100 0°C to 70°C
AD9884A/PCB
25°C
MQFP
S-128
MQFP
S-128
Evaluation Board
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified
temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
V
D,
PV
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4 V
PV
D
to V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
0.5 V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to –0.5 V
REFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
D
to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9884A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
AD9884A
Table I. Package Interconnections
Signal Type
Inputs
Name
R
AIN
G
AIN
B
AIN
HSYNC
COAST
CLAMP
SOGIN
CKEXT
CKINV
Function
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
Horizontal Sync Input
Clock Generator Coast Input (Optional)
External Clamp Input (Optional)
Sync On Green Slicer Input (Optional)
External Clock Input (Optional)
Sampling Clock Inversion (Optional)
Data Output, Red Channel, Port A
Data Output, Red Channel, Port B
Data Output, Green Channel, Port A
Data Output, Green Channel, Port B
Data Output, Blue Channel, Port A
Data Output, Blue Channel, Port B
Data Output Clock
Data Output Clock Complement
Horizontal Sync Output
Sync On Green Slicer Output
Serial Data I/O
Serial Interface Clock
Serial Port Address LSBs
Power-Down Control Input
Internal Reference Output
Reference Input
External Filter Connection
Main Power Supply
Digital Output Power Supply
Clock Generator Power Supply
Ground
Value
0.5 V to 1.0 V FS
0.5 V to 1.0 V FS
0.5 V to 1.0 V FS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
0.5 V to 1.0 V FS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
1.25 V
1.25 V
±
10%
3.3 V
±
10%
Package Pin
7
15
22
40
41
28
14
44
27
105–112
95–102
85–92
75–82
65–72
55–62
115
116
117
118
29
30
31, 32
125
126
127
45
Outputs
D
R
A
7-0
D
R
B
7-0
D
G
A
7-0
D
G
B
7-0
D
B
A
7-0
D
B
B
7-0
DATACK
DATACK
HSOUT
SOGOUT
Control
SDA
SCL
A
0
, A
1
PWRDN
REFOUT
REFIN
FILT
V
D
V
DD
PV
D
GND
Analog Interface
Power Supply
4, 8, 10, 11, 16, 18, 19, 23, 25,
124, 128
2.5 V to 3.3 V
±
10% 54, 64, 74, 84, 94, 104, 114, 120
3.3 V
±
10%
33, 34, 43, 48, 50
0V
5, 6, 9, 12, 13, 17, 20, 21, 24, 26,
35, 39, 42, 47, 49, 51, 52, 53, 63,
73, 83, 93, 103, 113, 119, 121,
122, 123
1–3, 36–38, 46
No Connect
NC
–4–
REV. C
