Data Sheet
FEATURES
2.5 GSPS internal clock speed
Integrated 12-bit DAC
Frequency tuning resolution to 135 pHz
16-bit phase tuning resolution
12-bit amplitude scaling
Programmable modulus
Automatic linear and nonlinear frequency sweeping
capability
32-bit parallel datapath interface
8 frequency/phase offset profiles
Phase noise: −128 dBc/Hz (1 kHz offset at 978 MHz)
Wideband SFDR < −57 dBc
Serial or parallel input/output control
1.8 V/3.3 V power supplies
Software and hardware controlled power-down
88-lead LFCSP package
PLL REF CLK multiplier
Phase modulation capability
Amplitude modulation capability
Multichip synchronization
2.5 GSPS Direct Digital Synthesizer
with 12-Bit DAC
AD9915
FUNCTIONAL BLOCK DIAGRAM
AD9915
HIGH SPEED PARALLEL
MODULATION
PORT
LINEAR
SWEEP
BLOCK
2.5GSPS DDS CORE
12-BIT DAC
REF CLK
MULTIPLIER
TIMING AND CONTROL
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
Polar modulator
Fast frequency hopping
Figure 1.
Rev. F
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10837-001
SERIAL OR PARALLEL
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AD9915* PRODUCT PAGE QUICK LINKS
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REFERENCE MATERIALS
Press
•
Analog Devices Advances RF and Microwave Designs
from Bits to Antenna and Back at IMS2012
•
Analog Devices Unveils Industry's Fastest 12-bit, Direct
Digital Synthesizers for Frequency-Agile Wireless
Applications
Product Selection Guide
•
RF Source Booklet
EVALUATION KITS
•
AD9915 Evaluation Board
DOCUMENTATION
Application Notes
•
AN-1254: Synchronizing Multiple AD9915 DDS-Based
Synthesizers
•
AN-953: Direct Digital Synthesis (DDS) with a
Programmable Modulus
Data Sheet
•
AD9915: 2.5 GSPS Direct Digital Synthesizer with 12-Bit
DAC Data Sheet
User Guides
•
AD9914/AD9915 Evaluation Board User Guide
DESIGN RESOURCES
•
AD9915 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD9915 EngineerZone Discussions.
TOOLS AND SIMULATIONS
•
AD9915 IBIS Model
SAMPLE AND BUY
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AD9915
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings ............................................................ 8
Thermal Performance .................................................................. 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Single Tone Mode ....................................................................... 17
Profile Modulation Mode .......................................................... 17
Digital Ramp Modulation Mode .............................................. 17
Parallel Data Port Modulation Mode....................................... 17
Programmable Modulus Mode ................................................. 17
Mode Priority .............................................................................. 18
Functional Block Detail ................................................................. 19
DDS Core..................................................................................... 19
Data Sheet
12-Bit DAC Output .................................................................... 20
DAC Calibration Output ........................................................... 20
Reconstruction Filter ................................................................. 20
Clock Input (REF_CLK/REF_CLK) ........................................ 21
PLL Lock Indication .................................................................. 22
Output Shift Keying (OSK) ....................................................... 22
Digital Ramp Generator (DRG) ............................................... 23
Power-Down Control ................................................................ 27
Programming and Function Pins ................................................. 28
Serial Programming ....................................................................... 31
Control Interface—Serial Input/Output ................................. 31
General Serial Input/Output Operation.................................. 31
Instruction Byte .......................................................................... 31
Serial Input/Output Port Pin Descriptions ............................. 31
Serial Input/Output Timing Diagrams .................................... 32
MSB/LSB Transfers .................................................................... 32
Parallel Programming (8-/16-Bit) ................................................ 33
Multiple Chip Synchronization .................................................... 34
Register Map and Bit Descriptions .............................................. 36
Register Bit Descriptions ........................................................... 41
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
REVISION HISTORY
6/2016—Rev. E to Rev. F
Changes to Figure 17 and Figure 19............................................. 14
1/2016—Rev. D to Rev. E
Changes to DDS Core Section ...................................................... 19
Change to Figure 30 ....................................................................... 19
Updated Outline Dimensions ....................................................... 47
1/2014—Rev. C to Rev. D
Change to Maximum DAC Calibration Time Parameter ........... 5
Change to Figure 23 ....................................................................... 15
Changes to DAC Calibration Output Section............................. 20
Change to Address 0x02, Table 16................................................ 36
Changes to Table 19 ........................................................................ 43
11/2013—Rev. B to Rev. C
Changes to Table 2 ............................................................................ 5
Changes to Programming and Function Pins Section .............. 30
7/2013—Rev. A to Rev. B
Change to CMOS Logic Outputs Parameter, Table 1 ...................4
Changes to Table 2.............................................................................7
Changes to DDS Core Section ...................................................... 19
Changes to Phase-Locked Loop (PLL) Multiplier Section ....... 21
Changed PLL Charge Pump Section to PLL Charge Pump/
Total Feedback Divider Section; Changes to Table 8, PLL
Loop Filter Components Section, and Figure 34 ....................... 22
Change to Table 16 ......................................................................... 36
Changes to Bits [15:8], Table 19 ................................................... 43
8/2012—Rev. 0 to Rev. A
Changed External Clock Frequency from 3.5 GHz to 2.5 GHz
and Differential Input Voltage Unit from mV p-p to V p-p ........4
Updated Outline Dimensions ....................................................... 47
7/2012—Revision 0: Initial Version
Rev. F | Page 2 of 47
Data Sheet
GENERAL DESCRIPTION
The
AD9915
is a direct digital synthesizer (DDS) featuring a
12-bit DAC. The
AD9915
uses advanced DDS technology,
coupled with an internal high speed, high performance DAC
to form a digitally programmable, complete high frequency
synthesizer capable of generating a frequency agile analog
output sinusoidal waveform at up to 1.0 GHz. The
AD9915
enables fast frequency hopping and fine tuning resolution
(64-bit capable using programmable modulus mode). The
AD9915
also offers fast phase and amplitude hopping capability.
The frequency tuning and control words are loaded into the
AD9915
AD9915
via a serial or parallel input/output port. The
AD9915
also supports a user defined linear sweep mode of operation for
generating linear swept waveforms of frequency, phase or
amplitude. A high speed, 32-bit parallel data input port is
included, enabling high data rates for polar modulation
schemes and fast reprogramming of the phase, frequency,
and amplitude tuning words.
The
AD9915
is specified to operate over the extended industrial
temperature range (see the Absolute Maximum Ratings section).
AD9915
OSK
DRCTL
DRHOLD
DROVER
2
OUTPUT
SHIFT
KEYING
DIGITAL
RAMP
GENERATOR
DDS
AMPLITUDE (A)
DATA
θ
ROUTE
FREQUENCY (ω)
Asin (ωt +
θ)
AND
ω
PARTITION
CONTROL
CLOCK
SYSCLK
INTERNAL CLOCK TIMING
AND CONTROL
PHASE (θ)
A
Acos (ωt +
θ)
DAC
12-BIT
DAC_RSET
AOUT
AOUT
PS[2:0]
I/O_UPDATE
3
INTERNAL
PROGRAMMING
REGISTERS
REF_CLK
PLL
REF_CLK
32
D0 TO D31
F0 TO F3
SYNC_CLK
4
POWER-
DOWN
CONTROL
MULTICHIP
SYNCHRONIZATION
EXT_PWR_DWN
LOOP_FILTER
SYNC_IN
MASTER_RESET
SYNC_OUT
Figure 2. Detailed Block Diagram
Rev. F | Page 3 of 47
10837-002
AD9915
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, T
A
= 25°C, R
SET
= 3.3 kΩ,
I
OUT
= 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O
DVDD
AVDD (3.3 V)
AVDD (1.8 V)
SUPPLY CURRENT
I
DVDD_I/O
I
DVDD
I
AVDD(3.3V)
I
AVDD(1.8V)
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled
Base DDS Power, PLL Enabled
Linear Sweep Additional Power
Modulus Additional Power
Amplitude Scaler Additional
Power
Full Power-Down Mode
CMOS LOGIC INPUTS
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Input Current (I
INH
, I
INL
)
Maximum Input Capacitance (C
IN
)
CMOS LOGIC OUTPUTS
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
REF CLK INPUT CHARACTERISTICS
REF CLK Multiplier Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
REF CLK Multiplier Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
3.135
1.71
3.135
1.71
3.30
1.80
3.30
1.80
3.465
1.89
3.465
1.89
20
270
640
148
V
V
V
V
mA
mA
mA
mA
mW
mW
mW
mW
mW
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
See also the total power dissipation specifications
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2138
2237
28
20
138
400
2797
2890
Manual or automatic
Using either the power-down and enable register or the
EXT_PWR_DWN pin
616
mW
2.0
±60
3
2.7
DVDD_I/O
0.8
±200
V
V
µA
pF
V
V
At V
IN
= 0 V and V
IN
= DVDD_I/O
DVDD_I/O
0.4
I
OH
= 1 mA
I
OL
= 1 mA
REF CLK inputs must always be ac-coupled (both single-
ended and differential)
Single-ended, each pin
Differential
1
1.4
2
0.8
1
1.4
2
0.8
1.5
1.5
pF
kΩ
V
V p-p
pF
kΩ
V
V p-p
Single-ended, each pin
Differential
Rev. F | Page 4 of 47
