Changes to Pin Configuration and Function Descriptions
Section and Table 3 ........................................................................... 7
Changes to Table 5 .......................................................................... 15
Changes to Serial Interface Port Pin Description Section ........ 22
Changes to Figure 32 ...................................................................... 26
Added Exposed Pad Notation to Outline Dimensions ............. 27
Changes to Ordering Guide .......................................................... 27
5/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Electrical Specifications Section ................................ 3
Changes to Figure 3 .......................................................................... 9
Changes to Serial Port Operation Section ................................... 20
Inserted Figure 24, Figure 25, and Figure 26 .............................. 21
12/03—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD9952
ELECTRICAL SPECIFICATIONS
AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, DAC_R
SET
= 3.92 kΩ, external reference clock frequency = 400 MHz with
REFCLK multiplier disabled, unless otherwise noted. DAC output must be referenced to AVDD, not AGND.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Enabled @ 20×
Input Capacitance
Input Impedance
Duty Cycle
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power
1
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz A
OUT
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband Spurious-Free Dynamic Range (SFDR)
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
Narrow-Band SFDR
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±10 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±10 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±10 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±10 kHz)
Temp
Min
Typ
Max
Unit
Full
Full
Full
25°C
25°C
25°C
25°C
Full
1
20
4
3
1.5
50
35
–15
0
14
10
400
100
20
65
+3
MHz
MHz
MHz
pF
kΩ
%
%
dBm
Bits
mA
%FS
µA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
5
–10
15
+10
0.6
1
2
5
–105
–115
–132
AVDD −
0.5
73
67
62
58
52
87
89
91
93
85
87
89
91
83
85
87
89
81
83
85
87
AVDD + 0.5
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Rev. B | Page 3 of 28
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9952
Parameter
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High Z Load
Logic 0 Voltage, High Z Load
Propagation Delay
Output Duty Cycle Error
Rise/Fall Time, 5 pF Load
Toggle Rate, High Z Load
Output Jitter
2
COMPARATOR NARROW-BAND SFDR
10 MHz (±1 MHz)
10 MHz (±250 kHz)
10 MHz (±50 kHz)
10 MHz (±10 kHz)
70 MHz (±1 MHz)
70 MHz (±250 kHz)
70 MHz (±50 kHz)
70 MHz (±10 kHz)
110 MHz (±1 MHz)
110 MHz (±250 kHz)
110 MHz (±50 kHz)
110 MHz (±10 kHz)
140 MHz (±1 MHz)
140 MHz (±250 kHz)
140 MHz (±50 kHz)
140 MHz (±10 kHz)
160 MHz (±1 MHz)
160 MHz (±250 kHz)
160 MHz (±50 kHz)
160 MHz (±10 kHz)
CLOCK GENERATOR OUTPUT JITTER
3
5 MHz A
OUT
10 MHz A
OUT
40 MHz A
OUT
80 MHz A
OUT
120 MHz A
OUT
140 MHz A
OUT
160 MHz A
OUT
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
4
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V
5
(TCSU, TDSU)
Minimum Data Setup Time DVDD_I/O = 1.8 V
5
(TCSU, TDSU)
Minimum Data Hold Time (TDH)
Maximum Data Valid Time (TDV)
Temp
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Min
Typ
3
500
±12
30
1.6
0.4
3
±5
1
200
1
80
85
90
95
80
85
90
95
80
85
90
95
80
85
90
95
80
85
90
95
100
60
50
50
50
50
50
45
Max
Unit
pF
kΩ
µA
mV
V
V
ns
%
ns
MHz
ps rms
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Full
Full
Full
Full
Full
Full
Full
Full
25
7
7
2
3
5
0
25
Mbps
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 4 of 28
AD9952
Parameter
Wake-Up Time
6
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
Latency
I/O UPDATE to Frequency Change Propagation Delay
I/O UPDATE to Phase Offset Change Propagation Delay
I/O UPDATE to Amplitude Change Propagation Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION
8
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution
9
1
Temp
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Min
5
4
6
0
24
24
16
1.25
Typ
1
Max
Unit
ms
SYSCLK cycles
7
ns
ns
ns
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
V
V
V
V
µA
µA
pF
V
V
V
V
mW
mW
mW
MHz
MHz
SYSCLK cycles
0.6
2.2
3
2
1.35
0.4
2.8
0.4
162
150
20
62.5
100
±1
171
160
27
0.8
12
12
To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise
performance of the device.
2
Represents the cycle-to-cycle residual jitter from the comparator alone.
3
Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4
The maximum frequency of the serial I/O port refers to the maximum speed of the port during a write operation. During a register readback, the maximum port speed
is restricted to 2 Mbps.
5
Setup time refers to the TCSU (setup time of the falling edge of CS to the SCLK rising edge) and TDSU (setup time of the data change on SDIO to the SCLK rising edge).
6
Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions section). The longest time required is for the reference clock
multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used.
7
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
8
SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates
≥
50 MHz, the high speed sync enable bit, CFR2 [11], should be set.
9
This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
