Data Sheet
FEATURES
Dual 10-bit/12-bit, 100 MSPS ADC
SNR = 67 dB, f
IN
= 30.1 MHz
Dual 10-bit/12-bit, 170 MSPS DAC
ACLR = 74 dBc
5 channels of analog auxiliary input/output
Low power, <425 mW at maximum sample rates
Supports full and half-duplex data interfaces
Small 72-lead LFCSP lead-free package
10-/12-Bit,
Low Power, Broadband MxFE
AD9961/AD9963
FUNCTIONAL BLOCK DIAGRAM
AD9961/AD9963
TEMPERATURE
SENSOR
AUX
ADC
DLLFILT
CLKP
CLKN
DLL AND
CLOCK
DISTRIBUTION
AUX
DAC
AUX
DAC
INTERNAL
TXCLK
TXIQ/TXnRX
LPF
1/2/4/8
12-BIT
DAC
TXIP
TXIN
TXQP
TXQN
RXIP
RXIN
MUX
AUXIN1
AUXIO2
AUXIO3
APPLICATIONS
Wireless infrastructure
Picocell, femtocell basestations
Medical instrumentation
Ultrasound AFE
Portable instrumentation
Signal generators, signal analyzers
TXD[11:0]
DATA
ASSEMBLER
TRXCLK
TRXIQ
LPF
1/2
LPF
1/2/4/8
12-BIT
DAC
12-BIT
ADC
GENERAL DESCRIPTION
The AD9961/AD9963 are pin-compatible, 10-/12-bit, low
power MxFE® converters that provide two ADC channels with
sample rates of 100 MSPS and two DAC channels with sample
rates to 170 MSPS. These converters are optimized for transmit
and receive signal paths of communication systems requiring low
power and low cost. The digital interfaces provide flexible
clocking options. The transmit is configurable for 1×, 2×, 4×,
and 8× interpolation. The receive path has a bypassable 2×
decimating low-pass filter.
The AD9961 and AD9963 have five auxiliary analog channels.
Three are inputs to a 12-bit ADC. Two of these inputs can be
configured as outputs by enabling 10-bit DACs. The other
two channels are dedicated outputs from two independent
12-bit DACs.
The high level of integrated functionality, small size, and low
power dissipation of the AD9961/AD9963 make them well-
suited for portable and low power applications.
TRXD[11:0]
LPF
1/2
12-BIT
ADC
RXQP
RXQN
RESET
SDIO
SCLK
CS
REFERENCES
AND BIAS
TXCML
RXCML
REFIO
AUXADCREF
RXBIAS
AUX
DAC
SERIAL
PORT
LOGIC
AUX
DAC
LDO
VREGs
LDO_EN
DAC12A
DAC12B
Figure 1.
PRODUCT HIGHLIGHTS
1.
High Performance with Low Power Consumption.
The DACs operate on a single 1.8 V to 3.3 V supply.
Transmit path power consumption is <100 mW at
170 MSPS. Receive path power consumption is <350 mW
at 100 MSPS from 1.8 V supply. Sleep and power-down
modes are provided for low power idle periods.
High Integration.
The dual transmit and dual receive data converters, five
channels of auxiliary data conversion and clock generation
offer complete solutions for many modem designs.
Flexible Digital Interface.
The interface mates seamlessly to most digital baseband
processors.
2.
3.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
08801-001
AD9961/AD9963
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Serial Control Port .......................................................................... 20
General Operation of Serial Control Port ............................... 20
Sub Serial Interface Communications ..................................... 21
Configuration Registers ................................................................. 23
Configuration Register Bit Descriptions ................................. 24
Receive Path..................................................................................... 35
Receive ADC Operation ............................................................ 35
Decimation Filter and Digital Offset ....................................... 36
Transmit Path .................................................................................. 38
Interpolation Filters.................................................................... 38
Transmit DAC Operation .......................................................... 40
Data Sheet
Transmit DAC Outputs ............................................................. 42
Device Clocking.............................................................................. 45
Clock Distribution ..................................................................... 45
Driving the Clock Input ............................................................ 46
Clock Multiplication Using the DLL ....................................... 46
Configuring the Clock Doublers .............................................. 47
Digital Interfaces ............................................................................ 48
TRx Port Operation (Full-Duplex Mode) ............................... 48
Single ADC Mode ...................................................................... 48
Tx Port Operation (Full-Duplex Mode) ................................. 49
Half-Duplex Mode ..................................................................... 50
Auxiliary Converters ...................................................................... 52
Auxiliary ADC ............................................................................ 52
Conversion Clock ....................................................................... 52
Auxiliary DACs........................................................................... 53
Power Supplies ................................................................................ 55
Power Supply Configuration Examples ................................... 55
Power Dissipation....................................................................... 55
Example Start-Up Sequences ........................................................ 58
Configuring the DLL ................................................................. 58
Configuring the Clock Doublers (DDLL)............................... 58
Sensing temperature with the AUXADC ................................ 58
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 59
REVISION HISTORY
8/12—Rev. 0 to Rev. A
Changes to Table 15 ........................................................................ 24
Changes to Figure 65 ...................................................................... 45
Added DLL Duty Cycle Caution Section .................................... 46
Changes to Table 22 ........................................................................ 47
Changes to Figure 93 and Power Supply Configuration
Examples Section ............................................................................ 55
Added Example Start-Up Sequences Section ............................. 58
Updated Outline Dimensions ....................................................... 59
7/10—Revision 0: Initial Version
Rev. A | Page 2 of 60
Data Sheet
SPECIFICATIONS
AD9961/AD9963
T
MIN
to T
MAX
, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, I
OUTFS
= 2 mA, DAC sample rate = 125 MSPS. No
interpolation, unless otherwise noted.
Table 1. Tx Path Specifications
Parameter
TxDAC DC CHARACTERISTICS
Resolution
Differential Nonlinearity
Gain Variation (Internal Reference)
Gain Matching
Offset Error
Full-Scale Output Current (Default Setting)
Output Compliance Range
TXVDD = 3.3 V, V
TXCML
= 0 V
TXVDD = 3.3 V, V
TXCML
= 0.5 V
TXVDD = 1.8 V, V
TXCML
= 0 V
Offset Temperature Drift
Gain Temperature Drift (Internal Reference)
Tx REFERENCE (DEFAULT REGISTER SETTINGS)
Internal Reference Voltage (REFIO)
Output Resistance
Temperature Drift
Adjustment Range (TXVDD = 3 V)
Adjustment Range (TXVDD = 1.8 V)
TxDAC AC CHARACTERISTICS
Maximum Update Rate
Spurious-Free Dynamic Range
f
OUT
= 5 MHz
f
OUT
= 20 MHz
Two-Tone Intermodulation Distortion
f
OUT1
= 5 MHz, f
OUT2
= 6 MHz
f
OUT1
= 20 MHz, f
OUT2
= 21 MHz
Noise Spectral Density
f
OUT
= 5 MHz
f
OUT
= 20 MHz
W-CDMA Adjacent Channel Leakage Ratio, 1 Carrier
f
DAC
= 122.88 MHz, f
OUT
= 11 MHz
Tx PATH DIGITAL FILTER INPUT RATES
SRRC (8× Interpolation Mode)
INT0 (4× Interpolation Mode)
INT1 (2× Interpolation Mode
Transmit DAC (1× Interpolation Mode)
Min
AD9961
Typ
Max
10
0.1
0.4
0.4
2.0
−0.5
+0.7
−0.5
0
±40
1.02
10
±25
0.8
0.8
175
78
68
85
78
−140
−136
70
21.875
43.75
87.5
175
21.875
43.75
87.5
175
1.2
REFIO
0.8
0.8
175
81
70
89
80
−145
−141
74
+1.0
+1.7
+0.8
−0.5
+0.7
−0.5
0
±40
1.02
10
±25
1.2
REFIO
Min
AD9963
Typ
Max
12
0.3
0.4
0.4
2.0
+1.0
+1.7
+0.8
Unit
Bits
LSB
%FSR
%FSR
%FSR
mA
V
V
V
ppm/°C
ppm/°C
V
kΩ
ppm/°C
V
V
MSPS
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBc
MHz
MHz
MHz
MHz
−10
−2.4
−0.03
+10
+2.4
+0.03
−10
−2.4
−0.03
+10
+2.4
+0.03
Rev. A | Page 3 of 60
AD9961/AD9963
Data Sheet
T
MIN
to T
MAX
, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, ADC sample rate = 100 MSPS. No
decimation, unless otherwise noted.
Table 2. Rx Path Specifications
Parameter
Rx ADC DC CHARACTERISTICS
Resolution
Differential Nonlinearity
Gain Error
Offset Error
Input Voltage Range
Input Capacitance
Rx ADC AC SPECIFICATIONS
Maximum Sample Rate
Spurious Free Dynamic Range
f
IN
= 10.1 MHz
f
IN
= 70.1 MHz
Two-Tone Intermodulation Distortion
f
IN1
= 10 MHz, f
IN2
= 11 MHz
f
IN1
= 29 MHz, f
IN2
= 32 MHz
Signal-to-Noise Ratio
f
IN
= 10.1 MHz
f
IN
= 30.1 MHz
f
IN
= 70.1 MHz
RXCML OUTPUTS
Output Voltage
Output Current
Rx DIGITAL FILTER CHARACTERISTICS
2× Decimation
Latency (ADC Clock Cycles)
Passband Ripple; f
OUT
/f
DAC
(0.4 × f
DATA
)
Stop-Band Rejection (f
DATA
± 0.4 × f
DATA
)
Min
AD9961
Typ
Max
10
0.1
±1
±0.5
1.56
8
100
77
75
78
76
61
60
60
1.4
0.1
100
77
73
82
80
68
67
66
1.4
0.1
Min
AD9963
Typ
Max
12
0.3
±1
±0.5
1.56
8
Unit
Bits
LSB
%FSR
%FSR
V p-p diff
pF
MSPS
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
V
mA
49
0.2
70
49
0.2
70
Cycles
f
OUT
/f
DAC
dB
Rev. A | Page 4 of 60
Data Sheet
Table 3. Auxiliary Converter Specifications
Parameter
AUXILIARY DAC12A/AUXDAC12B
Resolution
Differential Nonlinearity
Gain Error
Settling Time (±1%)
AUXILIARY DAC10A/DAC10B (Range = 0.5 V to 1.5 V)
Resolution
Differential Nonlinearity
Gain Error
Settling Time (±1%)
AUXILIARY ADC
Resolution
Differential Nonlinearity
Gain Error (Internal Reference)
Input Voltage Range
Maximum Sample Rate
Min
12
±0.8
±2.0
1
10
±1.0
±2.0
10
12
−1.0
−2.0
0
50
12
−1.0
−2.0
0
50
10
±1.0
±2.0
10
AD9961
Typ
Max
Min
12
±0.8
±2.0
1
AD9963
Typ
AD9961/AD9963
T
MIN
to T
MAX
, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, unless otherwise noted.
Max
Units
Bits
LSB
%
µs
Bits
LSB
%
µs
Bits
LSB
%
V
kHz
+1.0
+2.0
3.2
+1.0
+2.0
3.2
Rev. A | Page 5 of 60
