110 MSPS/140 MSPS Analog Interface for
Flat Panel Displays
AD9985
FEATURES
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
FUNCTIONAL BLOCK DIAGRAM
AUTO CLAMP
LEVEL ADJUST
8
R
AIN
CLAMP
A/D
R
OUTA
AUTO CLAMP
LEVEL ADJUST
8
G
AIN
CLAMP
A/D
G
OUTA
AUTO CLAMP
LEVEL ADJUST
8
B
AIN
HSYNC
COAST
CLAMP
A/D
B
OUTA
MIDSCV
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
CLAMP
FILT
SOGIN
SYNC
PROCESSING
AND CLOCK
GENERATION
DTACK
HSOUT
VSOUT
SOGOUT
REF
REF
BYPASS
04799-0-001
SCL
SDA
A0
SERIAL REGISTER AND
POWER MANAGEMENT
AD9985
Figure 1.
GENERAL DESCRIPTION
The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode rate
capability and full power analog bandwidth of 300 MHz
support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985 includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9985’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985 also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985 is
provided in a space-saving 80-lead LQFP surface-mount
plastic package and is specified over the –40°C to +85°C
temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9985
TABLE OF CONTENTS
Revision History ........................................................................... 2
Specifications..................................................................................... 3
Explanation of Test Levels........................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Design Guide................................................................................... 11
General Description................................................................... 11
Digital Inputs .............................................................................. 11
Input Signal Handling................................................................ 11
Hsync, Vsync Inputs................................................................... 11
Serial Control Port ..................................................................... 11
Output Signal Handling............................................................. 11
Clamping ..................................................................................... 11
RGB Clamping........................................................................ 11
YUV Clamping ....................................................................... 12
Gain and Offset Control............................................................ 12
Auto Offset .............................................................................. 12
Sync-on-Green............................................................................ 13
Clock Generation ....................................................................... 13
Power Management.................................................................... 14
Timing.......................................................................................... 15
Hsync Timing ............................................................................. 15
Coast Timing............................................................................... 15
2-Wire Serial Register Map ....................................................... 16
2-Wire Serial Control Register Detail Chip Identification... 19
PLL Divider Control .................................................................. 19
Clock Generator Control .......................................................... 19
Clamp Timing............................................................................. 20
Hsync Pulsewidth....................................................................... 20
Input Gain ................................................................................... 20
Input Offset ................................................................................. 20
Mode Control 1 .......................................................................... 21
2-Wire Serial Control Port........................................................ 26
Data Transfer via Serial Interface............................................. 26
Sync Slicer.................................................................................... 28
Sync Separator ............................................................................ 28
PCB Layout Recommendations ............................................... 29
Analog Interface Inputs ............................................................. 29
Power Supply Bypassing ............................................................ 29
PLL ............................................................................................... 30
Outputs (Both Data and Clocks).............................................. 30
Digital Inputs .............................................................................. 30
Voltage Reference ....................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering GuIde .......................................................................... 31
REVISION HISTORY
5/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD9985
SPECIFICATIONS
Analog Interface: V
D
= 3.3 V, V
DD
= 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted.
Table 1.
AD9985KSTZ-110
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew
t
BUFF
t
STAH
t
DHO
t
DAL
t
DAH
t
DSU
t
STASU
t
STOTSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Current, High (V
IH
)
Input Current, Low (V
IL
)
Input Capacitance
Temp
Test
Level
Min
Typ
8
±0.5
Max
Min
AD9985KSTZ-140
Typ
8
±0.5
Max
Unit
Bits
LSB
LSB
LSB
LSB
25°C
Full
25°C
Full
Full
I
VI
I
VI
VI
+1.25/–1.0
+1.35/–1.0
±0.5
±1.85
±2.0
Guaranteed
+1.35/−1.0
±1.45/−1.0
±0.5
±2.0
±2.3
Guaranteed
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
VI
VI
V
IV
IV
V
VI
VI
V
V
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
VI
VI
V
V
V
0.5
1.0
100
1
1
7
1.5
49
1.25
±50
110
−0.5
4.7
4.0
300
4.7
4.0
250
4.7
4.0
15
110
400
15
2.5
0.8
−1.0
+1.0
3
3
2.5
10
+2.0
140
−0.5
4.7
4.0
300
4.7
4.0
250
4.7
4.0
15
140
400
400
15
8.0
52
7
1.5
49
1.25
±50
1.0
100
0.5
1
1
8.0
52
46
46
V p-p
V p-p
ppm/°C
µA
µA
mV
% FS
% FS
V
ppm/°C
MSPS
MSPS
ns
µs
µs
ns
µs
µs
ns
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
µA
µA
pF
10
+2.0
110
12
700
1
1000
1
110
12
700
1
700
1
0.8
−1.0
+1.0
Rev. 0 | Page 3 of 32
AD9985
AD9985KSTZ-110
Parameter
DIGITAL OUTPUTS
Output Voltage, High (V
OH
)
Output Voltage, Low (V
OL
)
Duty Cycle DATACK
Output Coding
POWER SUPPLY
V
D
Supply Voltage
V
DD
Supply Voltage
P
VD
Supply Voltage
I
D
Supply Current (V
D
)
I
DD
Supply Current (V
DD
)
2
IP
VD
Supply Current (P
VD
)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
IN
= 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θ
JC
Junction-to-Case
Thermal Resistance
θ
JA
Junction-to-Ambient
Thermal Resistance
Temp
Full
Full
Full
Test
Level
VI
VI
IV
Min
V
D
−0.1
45
50
Binary
3.3
3.3
3.3
132
19
8
525
5
16.5
300
2
1.5
44
43
55
0.1
55
Typ
Max
Min
V
D
−0.1
45
50
Binary
3.3
3.3
3.3
180
26
11
650
5
16.5
300
2
1.5
43
42
55
0.1
55
AD9985KSTZ-140
Typ
Max
Unit
V
V
%
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
IV
IV
IV
V
V
V
VI
VI
VI
V
V
V
V
V
V
3.15
2.2
3.15
3.45
3.45
3.45
3.15
2.2
3.15
3.45
3.45
3.45
760
15
50
900
15
50
V
V
V
mA
mA
mA
mW
mA
mW
MHz
ns
ns
dB
dB
dBc
V
V
16
35
16
35
°C/W
°C/W
1
2
VCO range = 10, charge pump current = 110, PLL divider = 1693.
DATACK load = 15 pF, data load = 5 pF.
Rev. 0 | Page 4 of 32
AD9985
Table 2.
AD9985BSTZ-110
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew
t
BUFF
t
STAH
t
DHO
t
DAL
t
DAH
t
DSU
t
STASU
t
STAH
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Current, High (I
IH
)
Input Current, Low (I
IL
)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (V
OH
)
Output Voltage, Low (V
OL
)
Duty Cycle, DATACK
Output Coding
Temp
Test
Level
Min
Typ
8
±0.5
±0.5
Max
Unit
Bits
LSB
LSB
LSB
LSB
25°C
Full
25°C
Full
I
VI
I
VI
+1.25/−1.0
+1.5/−1.0
±1.85
±3.2
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
VI
VI
V
IV
IV
VI
VI
VI
VI
V
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
VI
VI
V
V
V
VI
VI
IV
0.5
1.0
100
1
2
7
1.5
49
1.25
±100
110
–0.5
4.7
4.0
300
4.7
4.0
250
4.7
15
110
400
15
2.5
0.8
−1.0
1.0
3
V
D
−0.1
45
50
Binary
0.1
55
10
+2.0
8.0
52
46
V p-p
V p-p
ppm/°C
µA
µA
mV
% FS
% FS
V
ppm/°C
MSPS
MSPS
ns
µs
µs
ns
µs
µs
ns
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
µA
µA
pF
V
V
%
110
12
700
1
1000
1
Rev. 0 | Page 5 of 32
