Low Noise Stereo Codec with
Recording and Playback Processing
ADAU1382
FEATURES
24-bit stereo audio ADC and DAC
400 mW speaker amplifier (into 8 Ω load)
Built-in sound engine for audio processing
Wind noise filter
Automatic level control (ALC)
5-band equalizer, including notch filter
Sampling rates from 8 kHz to 96 kHz
Stereo pseudo differential microphone input
Optional stereo digital microphone input pulse-density
modulation (PDM)
Stereo line output
PLL supporting a range of input clock rates
Analog and digital I/O 1.8 V to 3.3 V
Software control via SigmaStudio graphical user interface
Software-controllable, clickless mute
Software register and hardware pin standby mode
32-lead, 5 mm × 5 mm LFCSP
GENERAL DESCRIPTION
The ADAU1382 is a low power, 24-bit stereo audio codec. The
low noise DAC and ADC support sample rates from 8 kHz to
96 kHz. Low current draw and power saving modes make the
ADAU1382 ideal for battery-powered audio applications.
A configurable sound engine provides enhanced record and
playback processing to improve overall audio quality.
The record path includes two digital stereo microphone inputs
and an analog stereo input path. The analog inputs can be
configured for either a pseudo differential or a single-ended
stereo source. A dedicated analog beep input signal can be
mixed into any output path. The ADAU1382 includes a stereo
line output and speaker driver, which makes the device capable of
supporting dynamic speakers.
The serial control bus supports the I
2
C® or SPI protocols, and
the serial audio bus is programmable for I
2
S, left-justified, right-
justified, or TDM mode. A programmable PLL supports flexible
clock generation for all standard rates and available master clocks
from 11 MHz to 20 MHz.
DVDDOUT
APPLICATIONS
Digital still cameras
Digital video cameras
FUNCTIONAL BLOCK DIAGRAM
AGND1
AGND2
AVDD1
AVDD2
IOVDD
DGND
CM
REGULATOR
BEEP
PGA
ADAU1382
SOUND ENGINE
LMIC/LMICN/
MICD1
PGA
LMICP
LEFT
ADC
DECIMATION
FILTERS
WIND NOISE
NOTCH FILTER
RMIC/RMICN/
MICD2
PGA
RMICP
PDN
MICBIAS
MICROPHONE
BIAS
PLL
RIGHT
ADC
EQUALIZER
DIGITAL VOLUME
CONTROL
AUTOMATIC LEVEL
CONTROL
SERIAL DATA
INPUT/OUTPUT PORTS
I
2
C/SPI
CONTROL PORT
SPP
RIGHT
DAC
SPN
AOUTL
LEFT
DAC
OUTPUT
MIXER
AOUTR
ADC_SDATA/
GPIO1
LRCLK/GPIO3
DAC_SDATA/
GPIO0
BCLK/GPIO2
SCL/CCLK
MCKI
ADDR1/CLATCH
ADDR0/CDATA
SDA/COUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
08427-001
ADAU1382
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Record Side Performance Specifications ................................... 4
Output Side Performance Specifications ................................... 6
Power Supply Specifications........................................................ 8
Typical Power Management Measurements ............................. 9
Digital Filters ................................................................................. 9
Digital Input/Output Specifications......................................... 10
Digital Timing Specifications ................................................... 11
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution ................................................................................ 14
Pin Configuration and Function Descriptions ........................... 15
Typical Performance Characteristics ........................................... 17
System Block Diagrams ................................................................. 20
Theory of Operation ...................................................................... 24
Startup, Initialization, and Power ................................................. 25
Power-Up Sequence ................................................................... 25
Clock Generation and Management ........................................ 26
Enabling Digital Power to Functional Subsystems ................ 26
Setting Up the Sound Engine .................................................... 26
Power Reduction Modes............................................................ 26
Power-Down Sequence .............................................................. 26
Clocking and Sampling Rates ....................................................... 27
Core Clock ................................................................................... 27
Sampling Rates ............................................................................ 27
PLL ............................................................................................... 28
Record Signal Path.......................................................................... 30
Input Signal Path ........................................................................ 30
Analog-to-Digital Converters................................................... 31
Digital Automatic Level Control (ALC).................................. 31
Playback Signal Path ...................................................................... 32
Output Signal Paths ................................................................... 32
Digital-to-Analog Converters................................................... 32
Line Outputs ............................................................................... 32
Speaker Output ........................................................................... 32
Control Ports ................................................................................... 33
I
2
C Port ........................................................................................ 33
SPI Port ........................................................................................ 36
Memory and Register Access .................................................... 36
Serial Data Input/Output Ports .................................................... 38
TDM Modes ................................................................................ 38
General-Purpose Input/Outputs .................................................. 40
Sound Engine .................................................................................. 41
Signal Processing ........................................................................ 41
Processing Flow .......................................................................... 41
Programming .............................................................................. 41
Parameter Memory .................................................................... 41
Applications Information .............................................................. 42
Power Supply Bypass Capacitors .............................................. 42
GSM Noise Filter ........................................................................ 42
Grounding ................................................................................... 42
Speaker Driver Supply Trace (AVDD2) .................................. 42
Exposed Pad PCB Design ......................................................... 42
Control Register Map ..................................................................... 43
Clock Management, Internal Regulator, and PLL Control ... 44
Record Path Configuration ....................................................... 48
Serial Port Configuration .......................................................... 53
Audio Converter Configuration ............................................... 58
Playback Path Configuration .................................................... 63
Rev. 0 | Page 2 of 84
ADAU1382
Pad Configuration.......................................................................70
Digital Subsystem Configuration..............................................76
Outline Dimensions ........................................................................ 83
Ordering Guide ........................................................................... 83
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 3 of 84
ADAU1382
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C;
master clock (MCLK) = 12.288 MHz (f
S
= 48 kHz, 256 × f
S
mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz;
word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 2 mA; high level input voltage = 0.7 × IOVDD;
and low level input voltage = 0.3 × IOVDD. All power management registers are set to their default states.
RECORD SIDE PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
Noninverting Inputs PGA
(LMICP, RMICP)
Inverting Inputs PGA (LMICN, RMICN)
Test Conditions/Comments
All ADCs
Min
Typ
24
0.375
95
500
62
32
22
14
10
8
5
4
20
9
6
3.5
50
2
2
2
Max
Unit
Bits
dB
dB
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
All gain settings
0 dB gain
6 dB gain
10 dB gain
14 dB gain
17 dB gain
20 dB gain
26 dB gain
32 dB gain
0 dB
6 dB
10 dB
14 dB
−23 dB
20 dB
26 dB
32 dB
Beep Input PGA
SINGLE-ENDED MICROPHONE INPUT
TO ADC PATH
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Rev. 0 | Page 4 of 84
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
96
99.2
92
96.5
−88
−90
96
100
92
97
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
94
92
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
ADAU1382
Parameter
Left/Right Microphone PGA Gain
Range
Left/Right Microphone PGA Mute
Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
Test Conditions/Comments
AVDD = 3.3 V
AVDD = 3.3 V; mute set by Register
0x400E, Bit 1, and Register 0x400F, Bit 1
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V, 100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
Min
0
Typ
Max
32
Unit
dB
dB
mdB
mV
%
dB
dB
dB
−98
50
0.25
−1
−98
−55
−55
DIFFERENTIAL MICROPHONE INPUT TO
ADC PATH
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by Register
0x400E, Bit 1, and Register 0x400F, Bit 1
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V, 100 mV rms, 1 kHz
AVDD = 3.3 V, 100 mV rms, 20 kHz
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
−3 dBFS input, measured at AOUTL pin,
beep gain set to 0 dB
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
96
99.2
92
96.5
−84
−85
96
100
92
97
−98
50
0.25
−1
−85
−60
−45
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mdB
mV
%
dB
dB
dB
V rms
V rms (V p-p)
V rms (V p-p)
94
92
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Left/Right Microphone PGA Mute
Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
BEEP TO LINE OUTPUT PATH
Full-Scale Input Voltage (0 dB)
Total Harmonic Distortion + Noise
−88
−88
99
105
96
102
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Rev. 0| Page 5 of 84
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