INTEGRATED CIRCUITS
ADC0803/0804
CMOS 8-bit A/D converters
Product data
Supersedes data of 2001 Aug 03
2002 Oct 17
Philips
Semiconductors
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DESCRIPTION
The ADC0803 family is a series of three CMOS 8-bit successive
approximation A/D converters using a resistive ladder and
capacitive array together with an auto-zero comparator. These
converters are designed to operate with microprocessor-controlled
buses using a minimum of external circuitry. The 3-State output data
lines can be connected directly to the data bus.
The differential analog voltage input allows for increased
common-mode rejection and provides a means to adjust the
zero-scale offset. Additionally, the voltage reference input provides a
means of encoding small analog voltages to the full 8 bits of
resolution.
PIN CONFIGURATION
D
,
N PACKAGES
CS 1
RD 2
WR 3
CLK IN
4
20 V
CC
19 CLK R
18 D0
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
TOP VIEW
INTR 5
V
IN
(+) 6
V
IN
(–) 7
A GND
8
FEATURES
V
REF
/2 9
D GND 10
•
Compatible with most microprocessors
•
Differential inputs
•
3-State outputs
•
Logic levels TTL and MOS compatible
•
Can be used with internal or external clock
•
Analog input range 0 V to V
CC
•
Single 5 V supply
•
Guaranteed specification with 1 MHz clock
SL00016
Figure 1. Pin configuration
APPLICATIONS
•
Transducer-to-microprocessor interface
•
Digital thermometer
•
Digitally-controlled thermostat
•
Microprocessor-based monitoring and control systems
ORDERING INFORMATION
DESCRIPTION
20-pin plastic small outline (SO) package
20-pin plastic small outline (SO) package
20-pin plastic dual in-line package (DIP)
20-pin plastic dual in-line package (DIP)
TEMPERATURE
RANGE
0 to 70
°C
–40 to 85
°C
0 to 70
°C
–40 to +85
°C
ORDER CODE
ADC0803CD, ADC0804CD
ADC0803LCD, ADC0804LCD
ADC0803CN, ADC0804CN
ADC0803LCN, ADC0804LCN
TOPSIDE MARKING
ADC0803-1CD, ADC0804-1CD
ADC0803-1LCD, ADC0804-1LCD
ADC0803-1CN, ADC0804-1CN
ADC0803-1LCN, ADC0804-1LCN
DWG #
SOT163-1
SOT163-1
SOT146-1
SOT146-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
Supply voltage
Logic control input voltages
All other input voltages
T
amb
Operating temperature range
ADC0803LCD/ADC0804LCD
ADC0803LCN/ADC0804LCN
ADC0803CD/ADC0804CD
ADC0803CN/ADC0804CN
Storage temperature
Lead soldering temperature (10 seconds)
Maximum power dissipation
1
N package
D package
T
amb
= 25
°C
(still air)
1690
1390
mW
mW
PARAMETER
CONDITIONS
RATING
6.5
–0.3 to +16
–0.3 to (V
CC
+0.3)
–40 to +85
–40 to +85
0 to +70
0 to +70
–65 to +150
230
UNIT
V
V
V
°C
°C
°C
°C
°C
°C
T
stg
T
sld
P
D
NOTE:
1. Derate above 25
°C,
at the following rates: N package at 13.5 mW/°C; D package at 11.1 mW/°C.
2002 Oct 17
2
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
BLOCK DIAGRAM
V
IN
(+)
6
V
IN
(–)
7
M
+
–
+
9
V
REF
/2
LADDER AND
DECODER
8
A GND
AUTO ZERO
COMPARATOR
–
V
CC
20
D7 (MSB) (11)
D6
D5
D4
D3
D2
D1
D0 (LSB)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
OUTPUT
LATCHES
SAR
10
D GND
LE
OE
3
WR
8–BIT
SHIFT REGISTER
CLOCK
1
CS
S
INTR
FF
R
2
RD
Q
5
INTR
4
CLK IN
19
CLK R
SL00017
Figure 2. Block diagram
2002 Oct 17
3
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0 V, f
CLK
= 1 MHz, T
min
≤
T
amb
≤
T
max
, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
ADC0803 relative accuracy error (adjusted)
ADC0804 relative accuracy error (unadjusted)
R
IN
V
REF
/2 input resistance
3
Analog input voltage range
3
DC common-mode error
Power supply sensitivity
Control inputs
V
IH
V
IL
I
IH
I
IL
V
T
+
V
T
–
V
H
V
OL
V
OH
V
OL
Logical “1” input voltage
Logical “0” input voltage
Logical “1” input current
Logical “0” input current
V
CC
= 5.25 V
DC
V
CC
= 4.75 V
DC
V
IN
= 5 V
DC
V
IN
= 0 V
DC
–1
0.005
–0.005
2.0
15
0.8
1
V
DC
V
DC
µA
DC
µA
DC
3.5
2.1
2.0
0.4
2.4
V
DC
V
DC
V
DC
V
DC
V
DC
Over analog input voltage range
V
CC
= 5V
±10%
1
TEST CONDITIONS
Full-Scale adjusted
V
REF
/2 = 2.500 V
DC
V
CC
= 0 V
2
400
–0.05
1/16
1/16
680
V
CC
+0.05
1/8
Min
Typ
Max
0.50
1
UNIT
LSB
LSB
Ω
V
LSB
LSB
Clock in and clock R
Clock in positive-going threshold voltage
Clock in negative-going threshold voltage
Clock in hysteresis (V
T
+)–(V
T
–)
Logical “0” clock R output voltage
Logical “1” clock R output voltage
I
OL
= 360
µA,
V
CC
= 4.75 V
DC
I
OH
= –360
µA,
V
CC
= 4.75 V
DC
2.7
1.5
0.6
3.1
1.8
1.3
Data output and INTR
Logical “0” output voltage
Data outputs
INTR outputs
V
O
OH
I
OZL
I
OZH
I
SC
I
SC
I
CC
Logical “1” output voltage
3-State output leakage
3-State output leakage
+Output short-circuit current
–Output short-circuit current
Power supply current
I
OL
= 1.6 mA, V
CC
= 4.75 V
DC
I
OL
= 1.0 mA, V
CC
= 4.75 V
DC
I
OH
= –360
µA,
V
CC
= 4.75 V
DC
I
OH
= –10
µA,
V
CC
= 4.75 V
DC
V
OUT
= 0 V
DC
, CS = logical “1”
V
OUT
= 5 V
DC
, CS = logical “1”
V
OUT
= 0 V, T
amb
= 25
°C
V
OUT
= V
CC
, T
amb
= 25
°C
f
CLK
= 1 MHz, V
REF
/2 = OPEN,
CS = Logical “1”, T
amb
= 25
°C
4.5
9.0
12
30
3.0
3.5
2.4
4.5
–3
3
V
DC
C
µA
DC
µA
DC
mA
DC
mA
DC
mA
0.4
0.4
V
DC
V
DC
NOTES:
1. Analog inputs must remain within the range: –0.05
≤
V
IN
≤
V
CC
+ 0.05 V.
2. See typical performance characteristics for input resistance at V
CC
= 5 V.
3. V
REF
/2 and V
IN
must be applied after the V
CC
has been turned on to prevent the possibility of latching.
2002 Oct 17
4
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
Conversion time
f
CLK
Clock frequency
1
Clock duty cycle
1
CR
t
W(
WR)L
t
ACC
t
1H
, t
0H
t
W1
, t
R1
C
IN
Free-running conversion rate
Start pulse width
Access time
3-State control
INTR delay
Logic input=capacitance
Output
Output
INTR
RD
RD
WD
or RD
CS = 0, f
CLK
= 1 MHz
INTR tied to WR
CS = 0
CS = 0, C
L
= 100 pF
C
L
= 10 pF, R
L
= 10 kΩ
See 3-State test circuit
30
75
70
100
5
5
100
100
150
7.5
7.5
TO
FROM
TEST CONDITIONS
f
CLK
= 1 MHz
1
LIMITS
Min
66
0.1
40
1.0
Typ
Max
73
3.0
60
13690
UNIT
µs
MHz
%
conv/s
ns
ns
ns
ns
pF
pF
C
OUT
3-State output capacitance
NOTE:
1. Accuracy is guaranteed at f
CLK
= 1 MHz. Accuracy may degrade at higher clock frequencies.
FUNCTIONAL DESCRIPTION
These devices operate on the Successive Approximation principle.
Analog switches are closed sequentially by successive
approximation logic until the input to the auto-zero comparator
[ V
IN
(+)–V
IN
(–) ] matches the voltage from the decoder. After all bits
are tested and determined, the 8-bit binary code corresponding to
the input voltage is transferred to an output latch. Conversion begins
with the arrival of a pulse at the WR input if the CS input is low. On
the High-to-Low transition of the signal at the WR or the CS input,
the SAR is initialized, the shift register is reset, and the INTR output
is set high. The A/D will remain in the reset state as long as the CS
and WR inputs remain low. Conversion will start from one to eight
clock periods after one or both of these inputs makes a Low-to-High
transition. After the conversion is complete, the INTR pin will make a
High-to-Low transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion result. A read
(RD) operation (with CS low) will clear the INTR line and enable the
output latches. The device may be run in the free-running mode as
described later. A conversion in progress can be interrupted by
issuing another start command.
ANALOG OPERATION
Analog Input Current
The analog comparisons are performed by a capacitive charge
summing circuit. The input capacitor is switched between V
IN(+)
4
and V
IN(–)
, while reference capacitors are switched between taps on
the reference voltage divider string. The net charge corresponds to
the weighted difference between the input and the most recent total
value set by the successive approximation register.
The internal switching action causes displacement currents to flow
at the analog inputs. The voltage on the on-chip capacitance is
switched through the analog differential input voltage, resulting in
proportional currents entering the V
IN(+)
input and leaving the V
IN(–)
input. These transient currents occur at the leading edge of the
internal clock pulses. They decay rapidly so do not inherently cause
errors as the on-chip comparator is strobed at the end of the clock
period.
Input Bypass Capacitors and Source Resistance
Bypass capacitors at the input will average the charges mentioned
above, causing a DC and an AC current to flow through the output
resistance of the analog signal sources. This charge pumping action
is worse for continuous conversions with the V
IN(+)
input at full
scale. This current can be a few microamps, so bypass capacitors
should NOT be used at the analog inputs of the V
REF
/2 input for
high resistance sources (> 1 kΩ). If input bypass capacitors are
desired for noise filtering and a high source resistance is desired to
minimize capacitor size, detrimental effects of the voltage drop
across the input resistance can be eliminated by adjusting the full
scale with both the input resistance and the input bypass capacitor
in place. This is possible because the magnitude of the input current
is a precise linear function of the differential voltage.
Digital Control Inputs
The digital control inputs (CS, WR, RD) are compatible with
standard TTL logic voltage levels. The required signals at these
inputs correspond to Chip Select, START Conversion, and Output
Enable control signals, respectively. They are active-Low for easy
interface to microprocessor and microcontroller control buses. For
applications not using microprocessors, the CS input (Pin 1) can be
grounded and the A/D START function is achieved by a
negative-going pulse to the WR input (Pin 3). The Output Enable
function is achieved by a logic low signal at the RD input (Pin 2),
which may be grounded to constantly have the latest conversion
present at the output.
2002 Oct 17
5
