8-Bit Serial I O A D Converters with Multiplexer Options
January 1995
ADC0831 ADC0832 ADC0834 and ADC0838
8-Bit Serial I O A D Converters with Multiplexer Options
General Description
The ADC0831 series are 8-bit successive approximation
A D converters with a serial I O and configurable input mul-
tiplexers with up to 8 channels The serial I O is configured
to comply with the NSC MICROWIRE
TM
serial data ex-
change standard for easy interface to the COPS
TM
family of
processors and can interface with standard shift registers
or
mPs
The 2- 4- or 8-channel multiplexers are software configured
for single-ended or differential inputs as well as channel as-
signment
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero in-
put voltage value In addition the voltage reference input
can be adjusted to allow encoding any smaller analog volt-
age span to the full 8 bits of resolution
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Operates ratiometrically or with 5 V
DC
voltage
reference
No zero or full-scale adjust required
2- 4- or 8-channel multiplexer options with address
logic
Shunt regulator allows operation with high voltage
supplies
0V to 5V input range with single 5V power supply
Remote operation with serial digital data link
TTL MOS input output compatible
0 3 standard width 8- 14- or 20-pin DIP package
20 Pin Molded Chip Carrier Package (ADC0838 only)
Surface-Mount Package
Key Specifications
Y
Y
Y
Y
Y
Features
Y
Y
NSC MICROWIRE compatible direct interface to
COPS family processors
Easy interface to all microprocessors or operates
‘‘stand-alone’’
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
g
8 Bits
LSB and
g
1 LSB
5 V
DC
15 mW
32
ms
Typical Application
TL H 5583 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
COPS
TM
and MICROWIRE
TM
are trademarks of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL H 5583
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
Lead Temperature (Soldering 10 sec )
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Molded Chip Carrier Package
Vapor Phase (60 sec )
Infrared (15 sec )
ESD Susceptibility (Note 5)
260 C
300 C
215 C
220 C
2000V
2)
4 5 V
DC
to 6 3 V
DC
T
MIN
s
T
A
s
T
MAX
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Current into V
a
(Note 3)
Supply Voltage V
CC
(Note 3)
Voltage
Logic Inputs
Analog Inputs
Input Current per Pin (Note 4)
Package
Storage Temperature
Package Dissipation
at T
A
e
25 C (Board Mount)
15 mA
6 5V
b
0 3V to V
CC
a
0 3V
b
0 3V to V
CC
a
0 3V
g
5 mA
g
20 mA
Operating Ratings
(Notes 1
Supply Voltage V
CC
Temperature Range
ADC0831 8BCJ
ADC0831 4 8CCJ
ADC0832BIWM
ADC0831 2 4 8CIWM
ADC0831 2 4 8BCN
ADC0838BCV
ADC0831 2 4 8CCN
ADC0838CCV
ADC0831 2 4 8CCWM
b
65 C to
a
150 C
0 8W
b
40 C to
a
85 C
0 C to
a
70 C
Converter and Multiplexer Electrical Characteristics
The following specifications apply for V
CC
e
V
a e
V
REF
e
5V V
REF
s
V
CC
a
0 1V T
A
e
T
j
e
25 C and f
CLK
e
250 kHz
unless otherwise specified
Boldface limits apply from T
MIN
to T
MAX
BCJ BIWM
CIWM and CCJ Devices
Parameter
Conditions
Typ
(Note 12)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error
ADC0838BCV
ADC0831 2 4 8BCN
ADC0831 8BCJ
ADC0832BIWM
ADC0838CCV
ADC0831 2 4 8CCN
ADC0831 2 4 8CCWM
ADC0831 4 8CCJ
ADC0831 2 4 8CIWM
Minimum Reference
Input Resistance (Note 7)
Maximum Reference
Input Resistance (Note 7)
Maximum Common-Mode Input
Range (Note 8)
Minimum Common-Mode Input
Range (Note 8)
DC Common-Mode Error
g
BCV CCV CCWM BCN
and CCN Devices
Tested
Limit
(Note 13)
Design
Limit
(Note 14)
Units
Tested
Limit
(Note 13)
Design
Typ
Limit
(Note 12)
(Note 14)
V
REF
e
5 00 V
(Note 6)
g
g
g
g
g
g
LSB
g
1
g
1
g
1
g
1
g
1
g
1
g
1
g
1
35
35
13
59
V
CC
a
0 05
GND
b
0 05
g
35
35
13
54
13
59
kX
kX
V
V
LSB
V
CC
a
0 05
V
CC
a
0 05
GND
b
0 05
GND
b
0 05
g
g
g
2
Converter and Multiplexer Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e
V
a e
5V T
A
e
T
j
e
25 C and f
CLK
e
250 kHz unless otherwise specified
Boldface limits apply from T
MIN
to T
MAX
BCJ BIWM
CIWM and CCJ Devices
Parameter
Conditions
Typ
(Note 12)
Tested
Limit
(Note 13)
Design
Limit
(Note 14)
BCV CCV CCWM BCN
and CCN Devices
Typ
(Note 12)
Tested
Limit
(Note 13)
Design
Limit
(Note 14)
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS
(Continued)
Change in zero
error from V
CC
e
5V
to internal zener
operation (Note 3)
V
Z
internal
diode breakdown
(at V
a
) (Note 3)
Power Supply Sensitivity
I
OFF
Off Channel Leakage
Current (Note 9)
MIN
MAX
15 mA into V
a
V
CC
e
N C
V
REF
e
5V
1
15 mA into V
a
63
85
1
63
85
1
63
85
LSB
V
LSB
mA
mA
mA
mA
V
CC
e
5V
g
5%
On Channel
e
5V
Off Channel
e
0V
On Channel
e
0V
Off Channel
e
5V
g
g
g
g
g
g
b
0 2
b
1
a
0 2
a
1
b
0 2
b
1
a
0 2
a
1
b
0 2
a
0 2
b
0 2
a
0 2
b
1
a
1
b
1
a
1
I
ON
On Channel Leakage
Current (Note 9)
On Channel
e
0V
Off Channel
e
5V
On Channel
e
5V
Off Channel
e
0V
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical ‘‘1’’ Input
Voltage (Min)
V
IN(0)
Logical ‘‘0’’ Input
Voltage (Max)
I
IN(1)
Logical ‘‘1’’ Input
Current (Max)
I
IN(0)
Logical ‘‘0’’ Input
Current (Max)
V
OUT(1)
Logical ‘‘1’’ Output
Voltage (Min)
V
OUT(0)
Logical ‘‘0’’ Output
Voltage (Max)
I
OUT
TRI-STATE Output
Current (Max)
I
SOURCE
Output Source
Current (Min)
I
SINK
Output Sink Current (Min)
I
CC
Supply Current (Max)
ADC0831 ADC0834
ADC0838
ADC0832
Includes Ladder
Current
V
CC
e
5 25V
V
CC
e
4 75V
V
IN
e
5 0V
V
IN
e
0V
V
CC
e
4 75V
I
OUT
eb
360
mA
I
OUT
eb
10
mA
V
CC
e
4 75V
I
OUT
e
1 6 mA
V
OUT
e
0V
V
OUT
e
5V
V
OUT
e
0V
V
OUT
e
V
CC
b
0 1
20
08
0 005
b
0 005
20
08
0 005
b
0 005
20
08
1
b
1
V
V
mA
mA
1
b
1
1
b
1
24
45
04
b
3
b
0 1
24
45
04
b
3
a
3
b
7 5
24
45
04
b
3
a
3
b
6 5
V
V
V
mA
mA
mA
mA
mA
mA
01
b
14
3
b
6 5
01
b
14
16
09
23
80
25
65
16
09
23
90
25
65
80
25
65
3
AC Characteristics
The following specifications apply for V
CC
e
5V t
r
e
t
f
e
20 ns and 25 C unless otherwise specified
Parameter
Min
Max
Not including MUX Addressing Time
Min
Max
Conditions
Typ
(Note 12)
Tested
Limit
(Note 13)
10
400
8
40
60
250
Design
Limit
(Note 14)
Limit
Units
kHz
kHz
1 f
CLK
%
%
ns
f
CLK
Clock Frequency
t
C
Conversion Time
Clock Duty Cycle
(Note 10)
t
SET-UP
CS Falling Edge or
Data Input Valid to CLK
Rising Edge
t
HOLD
Data Input Valid
after CLK Rising Edge
t
pd1
t
pd0
CLK Falling
Edge to Output Data Valid
(Note 11)
t
1H
t
0H
Rising Edge of
CS to Data Output and
SARS Hi–Z
C
IN
Capacitance of Logic
Input
C
OUT
Capacitance of Logic
Outputs
90
C
L
e
100 pF
Data MSB First
Data LSB First
C
L
e
10 pF R
L
e
10k
(see TRI-STATE Test Circuits)
C
L
e
100 pf R
L
e
2k
5
5
ns
650
250
125
500
1500
600
250
ns
ns
ns
ns
pF
pF
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2
All voltages are measured with respect to the ground plugs
Note 3
Internal zener diodes (6 3 to 8 5V) are connected from V
a
to GND and V
CC
to GND The zener at V
a
can operate as a shunt regulator and is connected
to V
CC
via a conventional diode Since the zener voltage equals the A D’s breakdown voltage the diode insures that V
CC
will be below breakdown when the device
is powered from V
a
Functionality is therefore guaranteed for V
a
operation even though the resultant voltage at V
CC
may exceed the specified Absolute Max of
6 5V It is recommended that a resistor be used to limit the max current into V
a
(See
Figure 3
in Functional Description Section 6 0)
Note 4
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
V
b
or V
IN
l
V
a
) the absolute value of current at that pin should be limited
to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four
Note 5
Human body model 100 pF discharged through a 1 5 kX resistor
Note 6
Total unadjusted error includes offset full-scale linearity and multiplexer errors
Note 7
Cannot be tested for ADC0832
Note 8
For V
IN
(
b
)
t
V
IN
(
a
) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater then the V
CC
supply Be careful during testing at low V
CC
levels (4 5V)
as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The
spec allows 50 mV forward bias of either diode This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 50 mV the
output code will be correct To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4 950 V
DC
over
temperature variations initial tolerance and loading
Note 9
Leakage current is measured with the clock not switching
Note 10
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of
these limits the minimum time the clock is high or the minimum time the clock is low must be at least 1
ms
The maximum time the clock can be high is 60
ms
The
clock can be stopped when low so long as the analog input voltage remains stable
Note 11
Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to
allow for comparator response time
Note 12
Typicals are at 25 C and represent most likely parametric norm
Note 13
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 14
Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels
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