ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with
voltage regulator
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. They convert the analog
input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal is allowed.
The device includes an internal voltage reference regulator. If the application requires that
the reference is driven via external sources the recommendation is to use one of the
ADC1004S030/040/050 family.
2. Features
10-bit resolution
Sampling rate up to 50 MHz
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input frequency range
(9.3 effective bits at 4.43 MHz full-scale input at f
clk
= 40 MHz)
No missing codes guaranteed
In-Range (IR) CMOS output
Levels TTL and CMOS compatible digital inputs
3 V to 5 V CMOS digital outputs
Low-level AC clock input signal allowed
Internal reference voltage regulator
Power dissipation only 235 mW (typical)
Low analog input capacitance, no buffer amplifier required
No sample-and-hold circuit required
3. Applications
High-speed analog-to-digital conversion for:
Video data digitizing
Radar
Transient signal analysis
Global Positioning System (GPS) receiver
modulators
®
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Cellular based stations
Barcode scanner
Medical imaging
4. Quick reference data
Table 1.
Quick reference data
V
CCA
= V3 to V4 = 4.75 V to 5.25 V; V
CCD
= V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
CCO
= V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
C to 70
C;
typical values measured at V
CCA
= V
CCD
= 5 V and V
CCO
= 3.3 V; C
L
= 15 pF and T
amb
= 25
C;
unless otherwise specified.
Symbol
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
INL
DNL
f
clk(max)
Parameter
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
integral non-linearity
f
clk
= 40 MHz;
ramp input
f
clk
= 40 MHz;
ramp input
Conditions
Min
4.75
4.75
3.0
-
-
-
-
-
30
40
50
-
Typ
5.0
5.0
3.3
30
16
1
0.8
0.5
-
-
-
235
Max
5.25
5.25
5.25
35
21
2
2.0
0.9
-
-
-
305
Unit
V
V
V
mA
mA
mA
LSB
LSB
MHz
MHz
MHz
mW
differential non-linearity f
clk
= 40 MHz;
ramp input
maximum clock
frequency
ADC1003S030TS
ADC1003S040TS
ADC1003S050TS
f
clk
= 40 MHz;
ramp input
P
tot
total power dissipation
5. Ordering information
Table 2.
Ordering information
Package
Name
ADC1003S030TS
ADC1003S040TS
ADC1003S050TS
SSOP28
SSOP28
SSOP28
Description
plastic shrink small outline package; 28 leads;
body width 5.3 mm
plastic shrink small outline package; 28 leads;
body width 5.3 mm
plastic shrink small outline package; 28 leads;
body width 5.3 mm
Version
Sampling
frequency
(MHz)
Type number
SOT341-1 30
SOT341-1 40
SOT341-1 50
ADC1003S030_040_050_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
2 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
6. Block diagram
V
CCA
3
DEC
5
CLK
1
V
CCD2
11
OE
10
REFERENCE
VOLTAGE
REGULATOR
RT
9
CLOCK DRIVER
2
TC
25 D9
24 D8
23 D7
R
lad
analog
voltage input
VI
8
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
CMOS
OUTPUTS
22 D6
21 D5
20 D4
19 D3
RM
7
18 D2
17 D1
16 D0
13
MSB
data outputs
LSB
RB
6
V
CCO
ADC1003S030/040/050
IN-RANGE LATCH
CMOS OUTPUT
26
IR
output
28
4
AGND
analog ground
12
DGND2
digital ground
14
OGND
output ground
27
DGND1
V
CCD1
digital ground
014aaa321
Fig 1.
Block diagram
ADC1003S030_040_050_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
3 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
7. Pinning information
7.1 Pinning
CLK
TC
V
CCA
AGND
DEC
RB
RM
VI
RT
1
2
3
4
5
6
7
8
9
28 V
CCD1
27 DGND1
26 IR
25 D9
24 D8
23 D7
22 D6
21 D5
20 D4
19 D3
18 D2
17 D1
16 D0
15 n.c.
014aaa320
ADC1003S
050TS
OE 10
V
CCD2
11
DGND2 12
V
CCO
13
OGND 14
Fig 2.
Pin configuration
7.2 Pin description
Table 3.
Symbol
CLK
TC
V
CCA
AGND
DEC
RB
RM
VI
RT
OE
V
CCD2
DGND2
V
CCO
OGND
n.c.
D0
D1
D2
D3
ADC1003S030_040_050_3
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
clock input
two’s complement input (active LOW)
analog supply voltage (5 V)
analog ground
decoupling input
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
reference voltage TOP input
output enable input (CMOS level input, active LOW)
digital supply voltage 2 (5 V)
digital ground 2
supply voltage for output stages (3 V to 5 V)
output ground
not connected
data output; bit 0 (Least Significant Bit (LSB))
data output; bit 1
data output; bit 2
data output; bit 3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
4 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
Table 3.
Symbol
D4
D5
D6
D7
D8
D9
IR
DGND1
V
CCD1
Pin description
…continued
Pin
20
21
22
23
24
25
26
27
28
Description
data output; bit 4
data output; bit 5
data output; bit 6
data output; bit 7
data output; bit 8
data output; bit 9 (Most Significant Bit (MSB))
in-range data output
digital ground 1
digital supply voltage 1 (5 V)
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CCA
V
CCD
V
CCO
V
CC
Parameter
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
staged
V
CCA
V
CCD
V
CCA
V
CCO
V
CCD
V
CCO
V
I
V
i(clk)(p-p)
I
O
T
stg
T
amb
T
j
[1]
Conditions
[1]
[1]
[1]
Min
0.3
0.3
0.3
1.0
1.0
1.0
0.3
-
-
55
40
-
Max
+7.0
+7.0
+7.0
+1.0
+4.0
+4.0
+7.0
V
CCD
10
+150
+85
150
Unit
V
V
V
V
V
V
V
V
mA
C
C
C
input voltage
peak-to-peak clock input
voltage
output current
storage temperature
ambient temperature
junction temperature
referenced to
AGND
referenced to
DGND
The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between
0.3
V and +7.0 V provided that
the supply voltage differences
V
CC
are respected.
9. Thermal characteristics
Table 5.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to ambient
Conditions
in free air
Typ
110
Unit
K/W
ADC1003S030_040_050_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
5 of 19
