ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Rev. 02 — 12 August 2008
Product data sheet
1. General description
The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters
(ADC) optimized for a wide range of applications such as cellular infrastructures,
professional telecommunications, imaging, and digital radio. It converts the analog input
signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All
static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS
compatible and all outputs are CMOS compatible. A sine wave clock input signal can also
be used.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
12-bit resolution
Sampling rate up to 70 MHz
−3
dB bandwidth of 245 MHz
5 V power supplies and 3.3 V output power supply
Binary or twos complement CMOS outputs
In-range CMOS compatible output
TTL and CMOS compatible static digital inputs
TTL and CMOS compatible digital outputs
Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible
Power dissipation 550 mW (typical)
Low analog input capacitance (typical 2 pF), no buffer amplifier required
Integrated sample and hold amplifier
Differential analog input
External amplitude range control
Voltage controlled regulator included
−40 °C
to +85
°C
ambient temperature
3. Applications
High-speed analog-to-digital conversion for:
I
Cellular infrastructure
I
Professional telecommunication
I
Digital radio
I
Radar
I
Medical imaging
I
Fixed network
I
Cable modem
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
I
Barcode scanner
I
Cable Modem Termination System (CMTS)/
Data Over Cable Service Interface Specification (DOCSIS)
4. Quick reference data
Table 1.
Quick reference data
V
CCA
= V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V;
V
CCD
= V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; V
CCO
= V33 to V34 = 3.0 V to 3.6 V; AGND
and DGND shorted together; T
amb
=
−
40
°
C to 85
°
C; V
I(IN)(p-p)
−
V
I(INN)(p-p)
= 1.9 V;
V
ref
= V
CCA3
−
1.75 V; V
I(cm)
= V
CCA3
−
1.6 V; typical values measured at V
CCA
= V
CCD
= 5 V and
V
CCO
= 3.3 V, T
amb
= 25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
INL
DNL
Parameter
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
integral non-linearity
differential
non-linearity
f
clk
= 20 MHz
f
i
= 400 kHz
f
clk
= 20 MHz
f
i
= 400 kHz
f
clk
= 20 MHz
f
i
= 400 kHz
(no missing code
guaranteed)
ADC1206S040H
ADC1206S055H
ADC1206S070H
P
tot
total power dissipation
f
clk
= 55 MHz
f
i
= 20 MHz
Conditions
Min
4.75
4.75
3.0
-
-
-
-
-
Typ
5.0
5.0
3.3
78
27
3
±2.6
±0.5
Max
5.25
5.25
3.6
87
30
4
±4.5
Unit
V
V
V
mA
mA
mA
LSB
+1.1
−
0.95 LSB
f
clk(max)
maximum clock
frequency
40
55
70
-
-
-
-
550
-
-
-
660
MHz
MHz
MHz
mW
5. Ordering information
Table 2.
Ordering information
Package
Name
ADC1206S040H
ADC1206S055H
ADC1206S070H
QFP44
QFP44
QFP44
Description
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
Version
Sampling
frequency
(MHz)
Type number
SOT307-2 40
SOT307-2 55
SOT307-2 70
ADC1206S040_055_070_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 August 2008
2 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
6. Block diagram
V
CCA1
2
6 to 10,13,14,16
n.c.
12
V
CCA3
3
V
CCA4
CLKN
41
35
CLK
36
V
CCD1
37
V
CCD2
15
OTC
18
CE
19
FSREF
Vref
REFERENCE
CLOCK DRIVER
ADC1206S040/055/070
V
ref
11
21 D11
22 D10
23 D9
AMP
24 D8
25 D7
MSB
INN
IN
43
42
ANALOG - TO -
DIGITAL
CONVERTER
LATCHES
CMOS
OUTPUTS
26 D6
27 D5
28 D4
29 D3
data outputs
sample -
and - hold
SH
39
30 D2
31 D1
32 D0
33
LSB
V
CCO
CMADC
1
5
CMADC
REFERENCE
OVERFLOW/UNDERFLOW
LATCH
CMOS OUTPUT
20
IR
DEC
44
4
40
38
17
34
AGND1
AGND3
AGND4
DGND1
DGND2
OGND
014aaa385
Fig 1. Block diagram.
ADC1206S040_055_070_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 August 2008
3 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
7. Pinning information
7.1 Pinning
38 DGND1
44 AGND1
41 V
CCA4
40 AGND4
34 OGND
33 V
CCO
32 D0
31 D1
30 D2
29 D3
28 D4
27 D5
26 D6
25 D7
24 D8
23 D9
FSREF 12
n.c. 13
n.c. 14
V
CCD2
15
n.c. 16
DGND2 17
OTC 18
CE 19
IR 20
D11 21
D10 22
014aaa383
37 V
CCD1
CMADC
V
CCA1
V
CCA3
AGND3
DEC
n.c.
n.c.
n.c.
n.c.
1
2
3
4
5
6
7
8
9
ADC1206S070H
n.c. 10
V
ref
11
Fig 2.
Pin configuration
7.2 Pin description
Table 3.
Symbol
CMADC
V
CCA1
V
CCA3
AGND3
DEC
n.c.
n.c.
n.c.
n.c.
n.c.
V
ref
FSREF
n.c.
n.c.
V
CCD2
n.c.
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
regulator output common mode ADC input
analog supply voltage 1 (5 V)
analog supply voltage 3 (5 V)
analog ground 3
decoupling node
not connected
not connected
not connected
not connected
not connected
reference voltage input
full-scale reference output
not connected
not connected
digital supply voltage 2 (5 V)
not connected
ADC1206S040_055_070_2
35 CLKN
36 CLK
43 INN
39 SH
42 IN
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 August 2008
4 of 32
NXP Semiconductors
ADC1206S040/055/070
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Pin description
…continued
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Description
digital ground 2
control input twos complement output; active HIGH
chip enable input (CMOS level; active LOW)
in-range output
data output; bit 11 (Most Significant Bit (MSB))
data output; bit 10
data output; bit 9
data output; bit 8
data output; bit 7
data output; bit 6
data output; bit 5
data output; bit 4
data output; bit 3
data output; bit 2
data output; bit 1
data output; bit 0 (Least Significant Bit (LSB))
output supply voltage (3.3 V)
output ground
complementary clock input
clock input
digital supply voltage 1 (5 V)
digital ground 1
sample-and-hold enable input (CMOS level; active HIGH)
analog ground 4
analog supply voltage 4 (5 V)
analog input voltage
complementary analog input voltage
analog ground 1
Table 3.
Symbol
DGND2
OTC
CE
IR
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
V
CCO
OGND
CLKN
CLK
V
CCD1
DGND1
SH
AGND4
V
CCA4
IN
INN
AGND1
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CCA
V
CCD
V
CCO
∆V
CC
Parameter
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
V
CCA
−
V
CCD
V
CCD
−
V
CCO
V
CCA
−
V
CCO
Conditions
[1]
[1]
[1]
Min
−0.3
−0.3
−0.3
−1.0
−1.0
−1.0
Max
+7.0
+7.0
+7.0
+1.0
+4.0
+4.0
Unit
V
V
V
V
V
V
ADC1206S040_055_070_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 August 2008
5 of 32
