Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to
GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.
The ground return for the supply and signals.
For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground.
SCLK
SDATA
CS
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
V
IN
Analog input. This signal can range from 0V to V
A
.
Symbol
Description
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2
ADC121S021
Absolute Maximum Ratings
(Note
1, Note
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage V
A
Voltage on Any Digital Pin to GND
Voltage on Any Analog Pin to GND
Input Current at Any Pin (Note
3)
Package Input Current (Note
3)
Power Consumption at T
A
= 25°C
ESD Susceptibility (Note
5)
Human Body Model
Machine Model
Junction Temperature
Storage Temperature
−0.3V to 6.5V
−0.3V to 6.5V
−0.3V to (V
A
+0.3V)
±10 mA
±20 mA
See (Note
4)
3500V
300V
+150°C
−65°C to +150°C
Operating Ratings
Operating Temperature Range
(Note
1, Note 2)
−40°C
≤
T
A
≤
+85°C
+2.7V to +5.25V
−0.3V to +5.25V
0V to V
A
25 kHz to 20 MHz
up to 1Msps
V
A
Supply Voltage
Digital Input Pins Voltage Range
(regardless of supply voltage)
Analog Input Pins Voltage Range
Clock Frequency
Sample Rate
Package Thermal Resistance
Package
6-lead LLP
6-lead SOT-23
θ
JA
94°C / W
265°C / W
Soldering
process
must
comply
with
National
Semiconductor's Reflow Temperature Profile specifications.
Refer to www.national.com/packaging.
(Note
6)
ADC121S021 Converter Electrical Characteristics
(Note
7, Note 9)
The following specifications apply for V
A
= +2.7V to 5.25V, f
SCLK
= 1 MHz to 4 MHz, f
SAMPLE
= 50 ksps to 200 ksps, C
L
= 15 pF,
unless otherwise noted.
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Parameter
Conditions
Typical
Limits
(Note
9)
12
V
A
= +2.7V to +3.6V
INL
Integral Non-Linearity
V
A
= +4.75v to +5.25V
V
A
= +2.7V to +3.6V
DNL
Differential Non-Linearity
V
A
= +4.75v to +5.25V
V
OFF
GE
Offset Error
Gain Error
V
A
= +2.7v to +3.6V
V
A
= +4.75v to +5.25V
V
A
= +2.7 to +3.6V
V
A
= +4.75v to +5.25V
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz, −0.02 dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz, −0.02 dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz, −0.02 dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz, −0.02 dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz, −0.02 dBFS
V
A
= +5.25V
f
a
= 103.5 kHz, f
b
= 113.5 kHz
+0.45
−0.40
+0.55
−0.40
+0.45
−0.25
+0.60
−0.30
−0.18
−0.26
−0.75
−1.6
±1.5
±1.2
+1.0
−0.8
±1.0
Units
Symbol
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
Bits
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (max)
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
SNR
THD
SFDR
ENOB
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Effective Number of Bits
Intermodulation Distortion, Second
Order Terms
72
72.3
−83
85
11.7
−83
−82
11.3
70
70.8
dBFS (min)
dBFS (min)
dBFS
dB
Bits (min)
dBFS
dBFS
IMD
Intermodulation Distortion, Third Order V
A
= +5.25V
Terms
f
a
= 103.5 kHz, f
b
= 113.5 kHz
3
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ADC121S021
Symbol
FPBW
Parameter
-3 dB Full Power Bandwidth
V
A
= +5V
V
A
= +3V
Conditions
Typical
11
8
0 to V
A
Limits
(Note
9)
Units
MHz
MHz
V
ANALOG INPUT CHARACTERISTICS
V
IN
I
DCL
C
INA
Input Range
DC Leakage Current
Input Capacitance
Track Mode
Hold Mode
V
A
= +5.25V
V
A
= +3.6V
V
A
= +5V
V
A
= +3V
V
IN
= 0V or V
A
±0.1
2
I
SOURCE
= 200 µA
I
SOURCE
= 1 mA
I
SINK
= 200 µA
I
SINK
= 1 mA
V
A
− 0.07
V
A
− 0.1
0.03
0.1
±0.1
2
±10
4
0.4
30
4
2.4
2.1
0.8
0.4
±1
4
V
A
− 0.2
±1
µA (max)
pF
pF
V (min)
V (min)
V (max)
V (max)
µA (max)
pF (max)
V (min)
V
V (max)
V
µA (max)
pF (max)
DIGITAL INPUT CHARACTERISTICS
V
IH
V
IL
I
IN
C
IND
Input High Voltage
Input Low Voltage
Input Current
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
V
OH
V
OL
Output High Voltage
Output Low Voltage
I
OZH
, I
OZL
TRI-STATE® Leakage Current
C
OUT
TRI-STATE® Output Capacitance
Output Coding
POWER SUPPLY CHARACTERISTICS
V
A
Supply Voltage
V
A
= +5.25V,
f
SAMPLE
= 200 ksps
V
A
= +3.6V,
f
SAMPLE
= 200 ksps
f
SCLK
= 0 MHz, V
A
= +5.25V
f
SAMPLE
= 0 ksps
V
A
= +5.25V, f
SCLK
= 4 MHz,
f
SAMPLE
= 0 ksps
V
A
= +5.25V
V
A
= +3.6V
f
SCLK
= 0 MHz, V
A
= +5.25V
f
SAMPLE
= 0 ksps
V
A
= +5.25V, f
SCLK
= 4 MHz,
f
SAMPLE
= 0 ksps
Straight (Natural) Binary
2.7
5.25
1.5
0.40
500
60
7.9
1.5
2.6
315
14.7
4.3
2.8
1.2
V (min)
V (max)
mA (max)
mA (max)
nA
µA
mW (max)
mW (max)
µW
µW
Supply Current, Normal Mode
(Operational, CS low)
I
A
Supply Current, Shutdown (CS high)
Power Consumption, Normal Mode
(Operational, CS low)
P
D
Power Consumption, Shutdown (CS
high)
AC ELECTRICAL CHARACTERISTICS
f
SCLK
f
S
DC
t
ACQ
t
QUIET
Clock Frequency
Sample Rate
SCLK Duty Cycle
Minimum Time Required for Acquisition
(Note
10)
(Note
8)
(Note
8)
f
SCLK
= 4 MHz
50
1.0
4.0
50
200
40
60
350
50
MHz (min)
MHz (max)
ksps (min)
ksps (max)
% (min)
% (max)
ns (max)
ns (min)
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4
ADC121S021
Symbol
t
AD
t
AJ
Parameter
Aperture Delay
Aperture Jitter
Conditions
Typical
3
30
Limits
(Note
9)
Units
ns
ps
ADC121S021 Timing Specifications
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 1.0 MHz to 4.0 MHz, C
L
= 25 pF,
f
SAMPLE
= 50 ksps to 200 ksps,
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol
t
CS
t
SU
t
EN
t
ACC
t
CL
t
CH
t
H
Parameter
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA TRI-STATE
®
Disabled
(Note
11)
Data Access Time after SCLK Falling Edge (Note
12)
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
V
A
= +2.7V to +3.6V
V
A
= +4.75V to +5.25V
V
A
= +2.7V to +3.6V
V
A
= +4.75V to +5.25V
1
V
A
= +2.7V to +3.6V
V
A
= +4.75V to +5.25V
Conditions
Typical
Limits
10
10
20
40
20
0.4 x t
SCLK
0.4 x t
SCLK
7
5
25
6
25
5
Units
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
µs
t
DIS
SCLK Falling Edge to SDATA High Impedance (Note
13)
t
POWER-UP
Power-Up Time from Full Power-Down
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3:
When the input voltage at any pin exceeds the power supply (that is, V
IN
< GND or V
IN
> V
A
), the current at that pin should be limited to 10 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the V
A
pin. The current into the V
A
pin is limited by the Analog Supply Voltage specification.
Note 4:
The absolute maximum junction temperature (T
J
max) for this device is 150°C. The maximum allowable power dissipation is dictated by T
J
max, the
junction-to-ambient thermal resistance (θ
JA
), and the ambient temperature (T
A
), and can be calculated using the formula P
D
max = (T
J
max − T
A
) / θ
JA
. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5:
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms
Note 6:
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7:
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8:
This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9:
Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10:
Minimum Quiet Time required by bus relinquish and the start of the next conversion.
Note 11:
Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.
Note 12:
Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
Note 13:
t
DIS
is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted
to remove the effects of charging or discharging the output capacitance. This means that t
DIS
is the true bus relinquish time, independent of the bus loading.
