The ADC1241 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter On request the
ADC1241 goes through a self-calibration cycle that adjusts
positive linearity and full-scale errors to less than
g
LSB
each and zero error to less than
g
1 LSB The ADC1241
also has the ability to go through an Auto-Zero cycle that
corrects the zero error during every conversion
The analog input to the ADC1241 is tracked and held by the
internal circuitry and therefore does not require an external
sample-and-hold A unipolar analog input voltage range (0V
to
a
5V) or a bipolar range (
b
5V to
a
5V) can be accom-
modated with
g
5V supplies
The 13-bit word on the outputs of the ADC1241 gives a 2’s
complement representation of negative numbers The digi-
tal inputs and outputs are compatible with TTL or CMOS
logic levels
Key Specifications
Y
Y
Y
Y
Y
Y
Resolution
Conversion Time
Linearity Error
Zero Error
Positive Full Scale Error
Power Consumption
g
12 Bits plus Sign
13 8ms (max)
LSB (
g
0 0122%) (max)
g
1LSB (max)
g
1LSB (max)
70mW (max)
Features
Y
Y
Y
Y
Y
Y
Self-calibrating
Internal sample-and-hold
Bipolar input range with
g
5V supplies and single
a
5V reference
No missing codes over temperature
TTL MOS input output compatible
Standard 28-pin DIP
Applications
Y
Y
Y
Digital Signal Processing
High Resolution Process Control
Instrumentation
TRI-STATE is a registered trademark of National Semiconductor Corporation
Simplified Schematic
Connection Diagram
Dual-In-Line Package
TL H 10554 – 2
Top View
Order Number ADC1241CMJ
ADC1241CMJ 883 ADC1241BIJ or
ADC1241CIJ
See NS Package Number J28A
TL H 10554 – 1
C
1995 National Semiconductor Corporation
TL H 10554
RRD-B30M115 Printed in U S A
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
e
DV
CC
e
AV
CC
)
6 5V
b
6 5V
Negative Supply Voltage (V
b
)
b
0 3V to (V
CC
a
0 3V)
Voltage at Logic Control Inputs
Voltage at Analog Input (V
IN
) (V
b
b
0 3V) to (V
CC
a
0 3V)
AV
CC
-DV
CC
(Note 7)
0 3V
Absolute Maximum Ratings
(Notes 1
2)
Temperature Range
T
MIN
s
T
A
s
T
MAX
b
40 C
s
T
A
s
a
85 C
ADC1241BIJ ADC1241CIJ
ADC1241CMJ ADC1241CMJ 883
b
55 C
s
T
A
s
a
125 C
DV
CC
and AV
CC
Voltage
(Notes 6 7)
4 5V to 5 5V
b
4 5V to
b
5 5V
Negative Supply Voltage (V
b
)
Reference Voltage
(V
REF
Notes 6 7)
3 5V to AV
CC
a
50 mV
Operating Ratings
(Notes 1
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at 25 C (Note 4)
Storage Temperature Range
ESD Susceptability (Note 5)
Soldering Information
J Package (10 sec)
g
5 mA
g
20 mA
875 mW
b
65 C to
a
150 C
2000V
300 C
Converter Electrical Characteristics
The following specifications apply for V
CC
e
DV
CC
e
AV
CC
e a
5 0V V
b
e b
5 0V V
REF
e a
5 0V and f
CLK
e
2 0 MHz
unless otherwise specified
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C (Notes 6 7
and 8)
Symbol
Parameter
Conditions
Typical
Limit
(Note 9) (Notes 10 18)
Units
(Limit)
STATIC CHARACTERISTICS
Positive Integral
Linearity Error
Negative Integral
Linearity Error
Differential Linearity
Zero Error
Positive Full-Scale Error
Negative Full-Scale Error
C
REF
C
IN
V
IN
V
REF
Input Capacitance
Analog Input Capacitance
Analog Input Voltage
Power Supply
Sensitivity
Zero Error (Note 14) AV
CC
e
DV
CC
e
5V
g
5%
e
4 75V V
b
e b
5V
g
5%
V
Full-Scale Error
REF
Linearity Error
DYNAMIC CHARACTERISTICS
S (N
a
D) Unipolar Signal-to-Noise
a
Distortion
Ratio (Note 17)
S (N
a
D) Bipolar Signal-to-Noise
a
Distortion
Ratio (Note 17)
Unipolar Full Power Bandwidth (Note 17)
Bipolar Full Power Bandwidth (Note 17)
t
Ap
Aperture Time
Aperture Jitter
2
f
IN
e
1 kHz V
IN
e
4 85 V
p-p
f
IN
e
10 kHz V
IN
e
4 85 V
p-p
f
IN
e
1 kHz V
IN
e
g
4 85 V
p-p
f
IN
e
10 kHz V
IN
e
g
4 85 V
p-p
V
IN
e
0V to 4 85V
V
IN
e
g
4 85 V
p-p
72
72
76
76
32
25
100
100
dB
dB
dB
dB
kHz
kHz
ns
ps
rms
g
g
g
ADC1241BIJ
ADC1241CMJ CIJ
ADC1241BIJ
ADC1241CMJ CIJ
After Auto-Cal
(Notes 11 12)
After Auto-Cal
(Notes 11 12)
After Auto-Cal (Notes 11
12)
g
g
1
g
1
g
1
LSB(max)
LSB max
LSB(max)
LSB(max)
Bits(min)
LSB(max)
LSB(max)
LSB(max)
pF
pF
12
g
1
g
g
1
g
1
g
2
After Auto-Zero or Auto-Cal
(Notes 12 13)
After Auto-Cal (Note 12)
After Auto-Cal (Note 12)
80
65
0 05
V
CC
a
0 05
V
b
b
V(min)
V(max)
LSB
LSB
LSB
Digital and DC Electrical Characteristics
The following specifications apply for V
CC
e
DV
CC
e
AV
CC
e a
5 0V V
b
e b
5 0V V
REF
e a
5 0V and f
CLK
e
2 0 MHz
unless otherwise specified
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
(Notes 6 and 7)
Symbol
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
T
a
V
T
b
V
H
V
OUT(1)
Parameter
Logical ‘‘1’’ Input Voltage for
All Inputs except CLK IN
Logical ‘‘0’’ Input Voltage for
All Inputs except CLK IN
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
CLK IN Positive-Going
Threshold Voltage
CLK IN Negative-Going
Threshold Voltage
CLK IN Hysteresis
V
T
a
(min)
b
V
T
b
(max)
Logical ‘‘1’’ Output Voltage
V
CC
e
4 75V
I
OUT
e b
360
mA
I
OUT
e b
10
mA
V
CC
e
4 75V
I
OUT
e
1 6 mA
V
OUT
e
0V
V
OUT
e
5V
V
OUT
e
0V
V
OUT
e
5V
f
CLK
e
2 MHz CS
e
‘‘1’’
f
CLK
e
2 MHz CS
e
‘‘1’’
f
CLK
e
2 MHz CS
e
‘‘1’’
b
0 01
Condition
V
CC
e
5 25V
V
CC
e
4 75V
V
IN
e
5V
V
IN
e
0V
Typical
(Note 9)
Limit
(Notes 10 18)
20
08
Units
(Limits)
V(min)
V(max)
mA(max)
mA(max)
V(min)
V(max)
V(min)
0 005
b
0 005
1
b
1
28
21
07
27
23
04
24
45
04
b
3
V(min)
V(min)
V(max)
mA(max)
mA(max)
mA(min)
mA(min)
mA(max)
mA(max)
mA(max)
V
OUT(0)
I
OUT
Logical ‘‘0’’ Output Voltage
TRI-STATE Output Leakage
Current
Output Source Current
Output Sink Current
DV
CC
Supply Current
AV
CC
Supply Current
V
b
Supply Current
0 01
b
20
3
b
6 0
I
SOURCE
I
SINK
DI
CC
AI
CC
I
b
20
1
28
28
80
2
6
6
3
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e a
5 0V V
b
e b
5 0V t
r
e
t
f
e
20 ns unless otherwise specified
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C (Notes 6 and 7)
Symbol
f
CLK
Parameter
Clock Frequency
05
40
Clock Duty Cycle
50
40
60
t
C
Conversion Time
f
CLK
e
2 0 MHz
t
A
t
Z
Acquisition Time
(Note 15)
Auto Zero Time
f
CLK
e
2 0 MHz
t
CAL
Calibration Time
f
CLK
e
2 0 MHz
t
W(CAL)L
t
W(WR)L
t
ACC
Calibration Pulse Width
Minimum WR Pulse Width
Maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
TRI-STATE Control (Delay
from Rising Edge of RD
to Hi-Z State)
Maximum Delay from Falling Edge of
RD or WR to Reset of INT
C
L
e
100 pF
50
R
L
e
1 kX
C
L
e
100 pF
85
ns(max)
(Note 16)
R
SOURCE
e
50X
f
CLK
e
2 0 MHz
27(1 f
CLK
)
13 5
7(1 f
CLK
)
35
26
13
1396
698
60
60
706
200
200
7(1 f
CLK
)
a
300 ns
26
27(1 f
CLK
)
a
300 ns
Conditions
Typical
(Note 9)
Limit
(Notes 10 18)
20
Units
(Limits)
MHz
MHz(min)
MHZ(max)
%
%(min)
%(max)
(max)
ms
(max)
ms
1 f
CLK
(max)
ms
1 f
CLK
ms
(max)
ns(min)
ns(min)
t
0H
t
1H
30
90
ns(max)
t
PD(INT)
100
175
ns(max)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
V
b
or V
IN
l
(AV
CC
or DV
CC
) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
(maximum junction temperature)
i
JA
(package
junction to ambient thermal resistance) and T
A
(ambient temperature) The maximum allowable power dissipation at any temperature is P
Dmax
e
(T
Jmax
b
T
A
)
i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For this device T
Jmax
e
125 C and the typical thermal resistance (i
JA
) of the
ADC1241 with CMJ BIJ and CIJ suffixes when board mounted is 47 C W
Note 5
Human body model 100 pF discharged through a 1 5 kX resistor
Note 6
Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than
50 mV
TL H 10554 – 3
This means that if AV
CC
and DV
CC
are minimum (4 75 V
DC
) and V
b
is maximum (
b
4 75 V
DC
) full-scale must be
s
4 8 V
DC
4
AC Electrical Characteristics
(Continued)
Note 7
A diode exists between AV
CC
and DV
CC
as shown below
TL H 10554 – 4
To guarantee accuracy it is required that the AV
CC
and DV
CC
be connected together to a power supply with separate bypass filters at each V
CC
pin
Note 8
Accuracy is guaranteed at f
CLK
e
2 0 MHz At higher and lower clock frequencies accuracy may degrade See curves in the Typical Performance
Characteristics Section
Note 9
Typicals are at T
J
e
25 C and represent most likely parametric norm
Note 10
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11
Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and
zero For negative linearity error the straight line passes through negative full scale and zero (See
Figures 1b
and
1c
)
Note 12
The ADC1241’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
g
0 20 LSB
Note 13
If T
A
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started see the typical performance characteristic curves
Note 14
After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes
Note 15
If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of t
A
therefore making the minimum t
A
e
6 clock periods and the maximum t
A
e
7 clock periods If the falling edge of the clock is synchronous to the rising edge of WR then t
A
will be exactly 6 5 clock
periods
Note 16
The CAL line must be high before any other conversion is started
Note 17
The specifications for these parameters are valid after an Auto-Cal cycle has been completed
Note 18
A military RETS electrical test specification is available on request At time of printing the ADC1241CMJ 883 RETS specification complies fully with the
