ADC14155QML 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter
June 15, 2009
ADC14155QML
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter
General Description
The ADC14155 is a high-performance CMOS analog-to-dig-
ital converter capable of converting analog input signals into
14-bit digital words at rates up to 155 Mega Samples Per
Second (MSPS). This converter uses a differential, pipelined
architecture with digital error correction and an on-chip sam-
ple-and-hold circuit to minimize power consumption and the
external component count, while providing excellent dynamic
performance. A unique sample-and-hold stage yields a full-
power bandwidth of 1.1 GHz. The ADC14155 operates from
dual +3.3V and +1.8V power supplies and consumes 967 mW
of power at 155 MSPS.
The separate +1.8V supply for the digital output interface al-
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 5 mW with
the clock input disabled, while still allowing fast wake-up time
to full operation.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14155 can
be operated with an external reference.
The ADC14155 can be configured for either single-ended or
differential operation. Clock mode (differential versus single-
ended) and output data format (offset binary versus 2's com-
plement) are pin-selectable. A duty cycle stabilizer maintains
performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead thermally ehanced
mult-layer ceramic quad package and operates over the mil-
itary temperature range of -55°C to +125°C.
Features
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Total Ionizing Dose
100 krad(Si)
Single Event Latch-up
120 MeV-cm
2
/mg
1.1 GHz Full Power Bandwidth
Internal sample-and-hold circuit
Low power consumption
Internal precision 1.0V reference
Single-ended or Differential clock modes
Data Ready output clock
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V supply operation (+/- 10%)
Power-down mode
Offset binary or 2's complement output data format
48-pin Cer Quad package, (11.5mm x 11.5mm, 0.635mm
pin-pitch)
Key Specifications
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Resolution
Conversion Rate
SNR (f
IN
= 70 MHz)
SFDR (f
IN
= 70 MHz)
ENOB (f
IN
= 70 MHz)
Full Power Bandwidth
Power Consumption
14 Bits
155 MSPS
70.1 dBFS (typ)
82.3 dBFS (typ)
11.3 bits (typ)
1.1 GHz (typ)
967 mW (typ)
Applications
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High IF Sampling Receivers
Power Amplifier Linearization
Multi-carrier, Multi-mode Receivers
Test and Measurement Equipment
Communications Instrumentation
Radar Systems
Ordering Information
NS Part Number
ADC14155W-MLS
ADC14155WRQV
(Note 15)
TBD
SMD Part Number
NS Package Number
EL48A
EL48A
Package Description
48L Cer Quad
48L Cer Quad
© 2009 National Semiconductor Corporation
202107
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ADC14155QML
Block Diagram
20210702
Connection Diagram
20210714
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2
ADC14155QML
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
4
V
IN
−
Differential analog input pins. The differential full-scale input signal
level is two times the reference voltage with each input pin signal
centered on a common mode voltage, V
CM
.
Symbol
Equivalent Circuit
Description
5
V
IN
+
42, 43
46, 47
V
RP
V
RM
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between V
RP
and V
RN
as close to the pins as possible,
and a 10 µF capacitor should be placed in parallel.
V
RP
and V
RN
should not be loaded. V
RM
may be loaded to 1mA for
use as a temperature stable 1.5V reference.
It is recommended to use V
RM
to provide the common mode
voltage, V
CM
, for the differential analog inputs, V
IN
+ and V
IN
−.
This pin can be used as either the +1.0V internal reference voltage
output (internal reference operation) or as the external reference
voltage input (external reference operation).
To use the internal reference, V
REF
should be decoupled to AGND
with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In
this mode, V
REF
defaults as the output for the internal 1.0V
reference.
To use an external reference, overdrive this pin with a low noise
external reference voltage. The output impedance of the internal
reference at this pin is 9kΩ. Therefore, to overdrive this pin, the
impedance of the external reference source should be << 9kΩ.
This pin should not be used to source or sink current.
The full scale differential input voltage range is 2 * V
REF
.
The clock input pins can be configured to accept either a single-
ended or a differential clock input signal.
When the single-ended clock mode is selected through CLK_SEL/
DF (pin 8), connect the clock input signal to the CLK+ pin and
connect the CLK− pin to AGND.
When the differential clock mode is selected through CLK_SEL/DF
(pin 8), connect the positive and negative clock inputs to the CLK
+ and CLK− pins, respectively.
The analog input is sampled on the falling edge of the clock input.
44, 45
V
RN
48
V
REF
DIGITAL I/O
11
CLK+
12
CLK−
3
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ADC14155QML
Pin No.
Symbol
Equivalent Circuit
Description
This is a four-state pin controlling the input clock mode and output
data format.
CLK_SEL/DF = V
A
, CLK+ and CLK− are configured as a
differential clock input. The output data format is 2's complement.
CLK_SEL/DF = (2/3)*V
A
, CLK+ and CLK− are configured as a
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1/3)*V
A
, CLK+ is configured as a single-ended
clock input and CLK− should be tied to AGND. The output data
format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock
input and CLK− should be tied to AGND. The output data format is
offset binary.
This is a two-state input controlling Power Down.
PD = V
A
, Power Down is enabled. In the Power Down state only
the reference voltage circuitry remains active and power
dissipation is reduced.
PD = AGND, Normal operation.
Digital data output pins that make up the 14-bit conversion result.
D0 (pin 17) is the LSB, while D13 (pin 32) is the MSB of the output
word. Output levels are CMOS compatible.
Over-Range Indicator. This output is set HIGH when the input
amplitude exceeds the 14-bit conversion range (0 to 16383).
Data Ready Strobe. This pin is used to clock the output data. It has
the same frequency as the sampling clock. One word of data is
output in each cycle of this signal. The rising edge of this signal
should be used to capture the output data.
8
CLK_SEL/DF
7
PD
17-24,
27-32
33
D0–D13
OVR
34
DRDY
ANALOG POWER
2, 9, 37, 40,
41
1, 3, 6, 10, 38,
39
DIGITAL POWER
13
14
V
D
DGND
Positive digital supply pin. This pin should be connected to a quiet
+3.3V source and be bypassed to DGND with a 100 pF and 0.1 µF
capacitor located close to the power pin.
The ground return for the digital supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source of +1.8V and be bypassed to
DRGND with 100 pF and 0.1 µF capacitors located close to the
power pins.
The ground return for the digital output driver supply. These pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC's DGND or AGND pins.
See Section 6.0 (Layout and Grounding) for more details.
V
A
AGND
Positive analog supply pins. These pins should be connected to a
quiet +3.3V source and be bypassed to AGND with 100 pF and 0.1
µF capacitors located close to the power pins.
The ground return for the analog supply.
16, 25, 26, 36
V
DR
15, 35
DRGND
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4
ADC14155QML
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (V
A
, V
D
)
Supply Voltage (V
DR
)
|V
A
–V
D
|
Voltage on Any Input Pin
(Not to exceed 4.2V)
Voltage on Any Output Pin
(Not to exceed 2.35V)
Input Current at Any Pin other
than Supply Pins (Note 3)
Package Input Current (Note 3)
Max Junction Temp (T
J
)
ESD Rating
Human Body Model (Note 5)
Storage Temperature
−0.3V to 4.2V
−0.3V to 2.35V
Operating Ratings
Operating Temperature
Supply Voltage (V
A
, V
D
)
Output Driver Supply (V
DR
)
CLK
Clock Duty Cycle
Analog Input Pins
V
CM
|AGND-DGND|
(Notes 1, 2)
-55°C
≤
T
A
≤
+125°C
+3.0V to +3.6V
+1.6V to +2.0V
−0.05V to (V
A
+ 0.05V)
30/70 %
0V to 2.6V
1.4V to 1.6V
≤
100 mV
−0.3V to (V
A
+0.3V)
-0.3V to (V
DR
+0.2V)
±5 mA
±50 mA
+150°C
Class 2 (2500V)
−65°C to +150°C
≤
100mV
θ
JC
(°C/W)
(Heat Sink)
0.68
θ
J-T
(°C/W)
(Top of Package)
1.86
Package Thermal Resistance
Package
48L Cer
Quad
θ
JA
(°C/W)
21.8
Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
Subgroup
1
2
3
4
5
6
7
8A
8B
9
10
11
12
13
14
Description
Static tests at
Static tests at
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Setting time at
Setting time at
Setting time at
Temp (°C)
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
5
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