ADC1443D series
Dual channel 14-bit ADC; 125, 160 or 200 Msps;
JESD204B-compliant CGVxpress serial outputs
Rev. 1 — 28 September 2011
Objective data sheet
1. General description
The ADC1443D is a dual channel 14-bit Analog-to-Digital Converter (ADC) with
JESD204B-compliant CGVxpress interface optimized for high dynamic performance and
low power consumption at sample rates up to 200 Msps. Pipelined architecture and output
error correction ensure the ADC1443D is accurate enough to guarantee zero missing
codes over the entire operating range.
Supplied from a single 1.8 V source, the ADC1443D has serial outputs compliant with the
JESD204B standard over a configurable number of lanes (1 or 2). Multiple Device
Synchronization (MDS) allows sample-accurate synchronization of the data outputs of
multiple ADC devices. MDS, which is a unique feature of the CGV and CGVxpress
technology of NXP Semiconductors, guarantees a maximum skew of one clock period
between as many as 16 output lanes from up to eight ADC1443D devices.
An integrated Serial Peripheral Interface (SPI) allows easy configuration of the ADC. The
device also includes a programmable full-scale to allow a flexible input voltage range of
1 V (p-p) to 2 V (p-p).
With excellent dynamic performance from the baseband to input frequencies of up to
250 MHz or more, the ADC1443D is ideal for use in undersampled multi-carrier,
multi-standard communication system applications. Using a pipelined architecture, an
output error correction scheme ensures the ADC1443D is accurate enough to guarantee
zero missing codes over the entire operating range.
The ADC1443D200 is available in an HLQFN56 package (8 mm
8 mm outline). It is
supported with customer demo boards. This device is also available in a 12-bit resolution
variant with a choice of maximum sampling frequency (125, 160 or 200 Msps).
2. Features and benefits
Dual channel 14-bit resolution ADC
SNR = 72.5 dBFS (typical);
f
s
= 185 Msps; f
i
= 190 MHz
Sampling rate up to 200 Msps
SFDR = 86 dBc (typical); f
s
= 185 Msps;
f
i
= 190 MHz
JESD204B Device Subclass 0, 1 and 2
IMD3 = 88 dBc (typical); f
s
= 185 Msps;
f
i1
= 188.5 MHz; f
i2
= 191.5 MHz
compliant with harmonic clocking and
deterministic latency support
ADC Multiple Device Synchronization
Analog input bandwidth of 1 GHz
(MDS), CGVxpress feature
(typical)
Single 1.8 V supply
Typical power dissipation = 1.0 W;
f
s
= 200 Msps
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Pin to pin compatible with ADC1413D
series
Power-down and sleep modes
Industrial temperature range from
40 C
to +85
C
Serial Peripheral Interface (SPI) for
configuration control and status
monitoring
HLQFN56 package; 8 mm
8 mm
Two JESD204B serial output lanes, up
to 5 Gsps typical
Flexible input voltage range from
1 V (p-p) to 2 V (p-p) by 1 dB steps
Clock input divider from 1 to 8 supports
harmonic clocking
Duty Cycle Stabilizer (DCS)
Offset binary and two’s complement
output data
3. Applications
Wireless infrastructure: LTE, TD-LTE,
WiMAX, MC-GSM, CDMA, WCDMA,
TD-SCDMA
Software defined radio
Medical non-invasive scanners
Scientific particle detectors
Microwave backhaul transceivers
Aerospace and defense
communications and radar systems
Industrial signal analysis instruments
General-purpose high-speed
applications
4. Ordering information
Table 1.
Ordering information
f
s
(Msps)
200
160
125
Package
Name
ADC1443D200HD
ADC1443D160HD
ADC1443D125HD
HLQFN56
HLQFN56
HLQFN56
Description
Version
plastic thermal enhanced low profile quad flat package;
SOT935-2
no leads; 56 terminals; resin based; body 8
8
1.35 mm
plastic thermal enhanced low profile quad flat package;
SOT935-2
no leads; 56 terminals; resin based; body 8
8
1.35 mm
plastic thermal enhanced low profile quad flat package;
SOT935-2
no leads; 56 terminals; resin based; body 8
8
1.35 mm
Type number
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
2 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
5. Block diagram
SDIO
OTRA
OTRB
SCLK
SCS_N
ADC1443D
SPI
SYNCBP
SYNCBN
ENCODER 8-bit/10-bit A
SCRAMBLER A
SERIALIZER A
10-bit
CMLAP
INAP
T/H
INPUT
STAGE
INAM
ADC A CORE
PIPELINED
14-bit
FRAME ASSEMBLY
8-bit
8-bit
OUTPUT
BUFFER A
CMLAN
INBP
T/H
INPUT
STAGE
INBM
ADC B CORE
PIPELINED
14-bit
ENCODER 8-bit/10-bit B
SCRAMBLER B
SERIALIZER B
10-bit
OUTPUT
BUFFER B
8-bit
8-bit
CMLBP
CMLBN
REFERENCE
AND POWER
MANAGEMENT
CLOCK DIVIDER
AND DUTY CYCLE
STABILIZER
VCMA
VCMB
VDDA
AGND
VDDO
OGND
SYSREF CLKP
CLKM
aaa-000417
Fig 1.
Block diagram
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
3 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
6. Pinning information
6.1 Pinning
55 SYSREF (optional)
49 SYSREFN
48 SYSREFP
44 SYNCBN
56 VDDA
53 VDDA
50 VDDA
54 DNC
INAM
INAP
VCMA
DNC
DNC
AGND
CLKP
CLKM
AGND
1
2
3
4
5
6
7
8
9
47 DNC
terminal 1
index area
43 SYNCBP
42
41
40
39
38
37
45 OGND
46 VDDO
52 AGND
51 AGND
OGND
OGND
VDDO
CMLAP
CMLAN
VDDO
OGND
OGND
VDDO
CMLBN
CMLBP
VDDO
OGND
OGND
ADC1443D
HLQFN56
36
35
34
33
32
31
30
29
DNC 10
DNC 11
VCMB 12
INBP 13
INBM 14
15
16
17
18
19
20
21
22
23
24
25
26
27
VDDO
28
OGND
VDDA
VDDA
SCLK
SDIO
CFG2
SCR_EN
SCS_N
AGND
CFG0/OTRA
CFG1/OTRB
CFG3
DNC
Transparent top view
aaa-000424
Fig 2.
Pin configuration (SOT935-2)
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
4 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
6.2 Pin description
Table 2.
Symbol
INAM
INAP
VCMA
DNC
DNC
AGND
CLKP
CLKN
AGND
DNC
DNC
VCMB
INBP
INBM
VDDA
VDDA
SCLK
SDIO
SCS_N
AGND
DNC
SCR_EN
CFG0/OTRA
CFG1/OTRB
CFG2
CFG3
VDDO
OGND
OGND
OGND
VDDO
CMLBP
CMLBN
VDDO
OGND
OGND
VDDO
CMLAN
CMLAP
ADC1443D_SER
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Type
[1]
I
I
O
-
-
G
I
I
G
-
-
O
I
I
P
P
I
I/O
I
G
-
I
I/O
I/O
I/O
I/O
P
G
G
G
P
O
O
P
G
G
P
O
O
Description
channel A complementary analog input
channel A analog input
channel A output common voltage
do not connect
do not connect
analog ground
clock input
complementary clock input
analog ground
do not connect
do not connect
channel B output common voltage
channel B analog input
channel B complementary analog input
analog power supply
analog power supply
SPI clock
SPI data IO
SPI chip select
analog ground
do not connect
scrambler enable
configuration pin 0/OuT of Range A (OTRA)
configuration pin 1/OuT of Range B (OTRB)
configuration pin 2
configuration pin 3
digital output power supply
digital output ground
digital output ground
digital output ground
digital output power supply
channel B output
channel B complementary output
digital output power supply
digital output ground
digital output ground
digital output power supply
channel A complementary output
channel A output
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Objective data sheet
Rev. 1 — 28 September 2011
5 of 50
