Data Sheet
FEATURES
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
ADCMP606/ADCMP607
GENERAL DESCRIPTION
The
ADCMP606
and
ADCMP607
are very fast comparators
fabricated on XFCB2, an Analog Devices, Inc., proprietary
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from V
EE
− 0.5 V to
V
CCI
+ 0.2 V, low noise, CML-compatible output drivers, and
TTL-/CMOS-compatible latch inputs with adjustable hysteresis
and/or shutdown inputs.
The devices offer 1.25 ns propagation delay with 2.5 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.7 V input signal range. The
ADCMP607
features split
input/output supplies with no sequencing restrictions to
support a wide input signal range with independent output
swing control and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the
ADCMP607,
latch and programmable hysteresis features are
also provided with a unique single-pin control option.
The
ADCMP606
is available in a 6-lead SC70 package and the
ADCMP607
is available in a 12-lead LFCSP package.
Fully specified rail to rail at V
CCI
= 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to V
CCI
+ 0.2 V
CML-compatible output stage
1.25 ns propagation delay
50 mW at 2.5 V power supply
Shutdown pin
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
V
CCI
V
CCO
(ADCMP607 ONLY)
V
P
NONINVERTING
INPUT
Q OUTPUT
ADCMP606/
ADCMP607
V
N
INVERTING
INPUT
CML
Q OUTPUT
LE/HYS INPUT (ADCMP607 ONLY)
S
DN
INPUT (ADCMP607 ONLY)
Figure 1.
Rev. C
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05917-001
ADCMP606/ADCMP607
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Information ..................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Data Sheet
Applications Information .............................................................. 10
Power/Ground Layout and Bypassing ..................................... 10
CML-Compatible Output Stage ............................................... 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance ........................................................... 10
Comparator Propagation Delay Dispersion ............................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Points ................................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
4/16—Rev. B to Rev. C
Changes to Figure 4 and Table 6 ..................................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ..................................................... 7
Changes to Figure 12 and Figure 13............................................... 9
Changes to Comparator Hysteresis Section ................................ 11
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
8/07—Rev. 0 to Rev. A
Changes to Specifications Section .................................................. 3
Changes to Table 3 ............................................................................ 6
Changes to Ordering Guide .......................................................... 14
10/06—Revision 0: Initial Version
Rev. C | Page 2 of 14
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CCI
= V
CCO
= 2.5 V, T
A
= −40°C to +125°C, typical at T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
Resistance, Differential Mode
Resistance, Common Mode
Active Gain
Common-Mode Rejection Ratio
Symbol
V
P
, V
N
Test Conditions/Comments
V
CCI
= 2.5 V to 5.5 V
V
CCI
= 2.5 V to 5.5 V
V
CCI
= 2.5 V to 5.5 V
Min
−0.5
−0.2
−5.0
−5.0
−2.0
−0.1 V to V
CCI
−0.5 V to V
CCI
+ 0.5 V
A
V
CMRR
V
CCI
= 2.5 V, V
CCO
= 2.5 V,
V
CM
= −0.2 V to +2.7 V
V
CCI
= 2..5 V, V
CCO
= 5.5 V
R
HYS
= ∞
200
100
50
50
ADCMP606/ADCMP607
Typ
Max
V
CCI
+ 0.2
V
CCI
+ 0.2
V
CCI
+5.0
+5.0
2.0
Unit
V
V
V
mV
µA
µA
pF
kΩ
kΩ
dB
dB
dB
mV
V
OS
I
P
, I
N
C
P
, C
N
±2
1
700
350
85
Hysteresis
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP607 Only)
V
IH
V
IL
I
IH
I
IL
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage
Minimum Resistor Value
Latch Setup Time
Latch Hold Time
Latch-to-Output Delay
Latch Minimum Pulse Width
SHUTDOWN PIN CHARACTERISTICS
(ADCMP607 Only)
V
IH
V
IL
I
IH
I
IL
Sleep Time
Wake-Up Time
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
<0.1
Hysteresis is shut off
Latch mode guaranteed
V
IH
= V
CCO
V
IL
= 0.4 V
Current sink 0 µA
Hysteresis = 120 mV
V
OD
= 50 mV
V
OD
= 50 mV
V
OD
= 50 mV
V
OD
= 50 mV
2.0
−0.2
−6
−0.1
1.145
55
+0.4
V
CCO
+0.8
+6
+0.1
1.35
110
V
V
µA
mA
V
kΩ
ns
ns
ns
ns
t
S
t
H
t
PLOH
, t
PLOL
t
PL
1.25
75
−1.5
2.3
30
25
t
SD
t
H
V
OH
V
OL
Comparator is operating
Shutdown guaranteed
V
IH
= V
CCO
V
IL
= 0 V
10% output swing
V
OD
= 100 mV, output valid
V
CCO
= 2.5 V to 5.5 V
50 Ω terminate to V
CCO
50 Ω terminate to V
CCO
50 Ω terminate to V
CCO
2.0
−0.2
−6
+0.4
V
CCO
+0.6
+6
−0.1
<1
35
V
CCO
− 0.1
V
CCO
− 0.6
300
V
CCO
− 0.05
V
CCO
− 0.45
400
V
CCO
V
CCO
− 0.3
500
V
V
µA
mA
ns
ns
V
V
mV
Rev. C | Page 3 of 14
ADCMP606/ADCMP607
Parameter
AC PERFORMANCE
1
Rise Time/Fall time
Propagation Delay
Symbol
t
R
/t
F
t
PD
Test Conditions/Comments
10% to 90%,
V
CCI
= V
CCO
= 2.5 V to 5.5 V
V
CCI
= V
CCO
= 2.5 V to 5.5 V,
V
OD
= 50 mV
V
CCI
= V
CCO
= 2.5 V,
V
OD
= 10 mV
V
OD
= 50 mV
10 mV < V
OD
< 125 mV
−0.2 V < V
CM
< V
CC
+ 0.2 V
RJ
PW
MIN
T
DIFFSKEW
V
CCI
V
CCO
V
CCI
− V
CCO
V
CCI
− V
CCO
I
VCCI/VCCO
I
VCCI
I
VCCO
I
VCCO
P
D
P
D
PSRR
V
OD
= 200 mV, 0.5 V/ns
V
CCI
= V
CCO
= 5.5 V,
PW
OUT
= 90% of PW
IN
50%
2.5
2.5
−3.0
−6
11
16
0.5
10
16
30
90
−50
200
−30
Min
Typ
160
1.2
2.1
40
2.3
150
750
2
1.1
20
Data Sheet
Max
Unit
ps
ns
ns
ps
ns
ps
MHz
ps
ns
ps
5.5
5.5
+3.0
+6
21
26
1.5
18
25
55
150
800
30
V
V
V
V
mA
mA
mA
mA
mA
mW
mW
dB
µA
µA
Propagation Delay Skew—Rising to
Falling Transition
Overdrive Dispersion
Common-Mode Dispersion
Input Stage Bandwidth
RMS Random Jitter
Minimum Pulse Width
Output Skew Q to Q
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential (ADCMP607)
Positive Supply Current (ADCMP606)
Input Section Supply Current (ADCMP607)
Output Section Supply Current (ADCMP607)
Power Dissipation
Power Supply Rejection Ratio
Shutdown Mode I
CCI
Shutdown Mode I
CCO
1
T
PINSKEW
Operating
Nonoperating
V
CCI
= V
CCO
= 2.5 V
V
CCI
= V
CCO
= 5.5 V
V
CCI
= 2.5 V
V
CCO
= 2.5 V
V
CCO
= 5.5 V
V
CCI
= V
CCO
= 2.5 V
V
CCI
= V
CCO
= 5.5 V
V
CCI
= 2.5 V to 5 V
V
CCI
= V
CCO
= 2.5 V to 5 V
V
CCI
= V
CCO
= 2.5 V to 5 V
17.5
20.5
1.1
15.8
18
46
110
240
V
IN
= 100 mV square input at 50 MHz, V
CM
= 2.5 V, V
CCI
= V
CCO
= 2.5 V, unless otherwise noted.
Rev. C | Page 4 of 14
Data Sheet
TIMING INFORMATION
ADCMP606/ADCMP607
Figure 2 illustrates the
ADCMP606/ADCMP607
latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
LATCH ENABLE
t
S
t
H
t
PL
DIFFERENTIAL
INPUT VOLTAGE
V
IN
V
OD
V
N
± V
OS
t
PDL
Q OUTPUT
t
PLOH
50%
t
PDH
t
F
50%
Q OUTPUT
t
R
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
t
F
t
H
t
PDH
t
PDL
t
PL
t
PLOH
t
PLOL
t
R
t
S
V
OD
Symbol Description
Output fall time
Minimum hold time
Input to output high delay
Input to output low delay
Minimum latch enable pulse width
Latch enable to output high delay
Latch enable to output low delay
Output rise time
Minimum setup time
Voltage overdrive
Timing Description
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
Minimum time that the latch enable signal must be high to acquire an input signal
change.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
Difference between the input voltages V
A
and V
B
.
Rev. C | Page 5 of 14
05917-025
t
PLOL
