ADE7756_15,ADE7756_15 pdf中文资料,ADE7756_15引脚图,ADE7756

文档预览

FEATURES

High Accuracy, Supports IEC 687/1036

Less than 0.1% Error over a Dynamic Range of 1000 to 1

An On-Chip User Programmable Threshold for Line

Voltage SAG Detection and PSU Supervisory

The ADE7756 Supplies Sampled Waveform Data

(20 Bits) and Active Energy (40 Bits)

Digital Power, Phase and Input Offset Calibration

An On-Chip Temperature Sensor ( 3 C Typical after

Calibration)

An SPI-Compatible Serial Interface

A Pulse Output with Programmable Frequency

An Interrupt Request Pin (IRQ) and Status Register

Provide Early Warning of Register Overflow and

Other Conditions

Proprietary ADCs and DSP Provide High Accuracy

over Large Variations in Environmental Conditions

and Time

Reference 2.4 V 8% (20 ppm/ C Typical) with External

Overdrive Capability

Single 5 V Supply, Low Power (25 mW Typical)

GENERAL DESCRIPTION

Active Energy Metering IC

with Serial Interface

ADE7756*

The ADE7756 contains a sampled Waveform register and an

Active Energy register capable of holding at least five seconds of

accumulated power at full load. Data is read from the ADE7756

via the serial interface. The ADE7756 also provides a pulse output

(CF) with a frequency that is proportional to the active power.

In addition to real power information, the ADE7756 also provides

system calibration features, i.e., channel offset correction, phase

calibration, and power calibration. The part also incorporates a

detection circuit for short duration low voltage variations or sags.

The voltage threshold level and the duration (in number of half-

line cycles) of the variation are user programmable. An open drain

logic output (SAG) goes active low when a sag event occurs.

A zero crossing output (ZX) produces an output that is synchro-

nized to the zero crossing point of the line voltage. This output can

be used to extract timing or frequency information from the line.

The signal is also used internally to the chip in the calibration

mode. This permits faster and more accurate calibration of the

real power calculation. This signal is also useful for synchronization

of relay switching with a voltage zero crossing, thus improving

the relay life by reducing the risk of arcing.

The interrupt request output is an open drain, active low logic

output. The

IRQ

output will become active when the accumu-

lated real power register is half-full and also when the register

overflows. A status register indicates the nature of the interrupt.

The ADE7756 is available in 20-lead DIP and 20-lead

SSOP packages.

RESET

PGA

MULTIPLIER

ADC

TEMP

SENSOR

APGAIN[11:0]

ADC

2.4V

REFERENCE

LPF1

AGND

REF

IN/OUT

The ADE7756 is a high-accuracy electrical power measurement

IC with a serial interface and a pulse output. The ADE7756

incorporates two second-order sigma-delta ADCs, reference

circuitry, temperature sensor, and all the signal processing

required to perform active power and energy measurement.

FUNCTIONAL BLOCK DIAGRAM

DGND

HPF1

MULTIPLIER

LPF2

PHCAL[5:0]

ADE7756 REGISTERS

AND

SERIAL INTERFACE

DIN DOUT SCLK

CS IRQ

V1P

V1N

V2P

V2N

*U.S.

Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

ADE7756

SAG

APOS[11:0]

DFC

CFDIV[11:0]

CLKIN

CLKOUT

ADE7756

TABLE OF CONTENTS

–2–

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

ADE7756–SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8

PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8

POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8

ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13

LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14

Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Using the ADE7756 Interrupts with an MCU . . . . . . . . . 15

Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16

ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16

Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . .

Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . .

ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . .

ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . .

Integration Times under Steady Load . . . . . . . . . . . . . . .

POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . .

ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . .

ENERGY CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . .

CALIBRATING THE ENERGY METER . . . . . . . . . . . . .

Calculating the Average Active Power . . . . . . . . . . . . . . .

Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . .

Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . .

SUSPENDING THE ADE7756 FUNCTIONALITY . . . .

SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .

Communications Register . . . . . . . . . . . . . . . . . . . . . . . .

Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Status Register (04H)/Reset Interrupt

Status Register (05H) . . . . . . . . . . . . . . . . . . . . . . . . . .

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .

REV. 0

ADE7756

SPECIFICATIONS

Parameter

(AV

= DV

= 5 V

5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,

MIN

to T

MAX

= –40 C to +85 C, unless otherwise noted.)

A Version

B Version

Unit

kHz

Test Conditions/Comments

CLKIN = 3.579545 MHz

Channel 2 = 300 mV rms/60 Hz, Gain = 2

Over a Dynamic Range 1000 to 1

0.2

ANALOG INPUTS

Maximum Signal Levels

Input Impedance (dc)

Bandwidth

Gain Error

1, 2

390

0.3

156

DC Power Supply Rejection

Output Frequency Variation (CF)

0.3

Channel 1

Range = 1 V Full Scale

Range = 0.5 V Full Scale

Range = 0.25 V Full Scale

Channel 2

Gain Error Match

Channel 1

Range = 1 V Full Scale

Range = 0.5 V Full Scale

Range = 0.25 V Full Scale

Channel 2

Offset Error

Channel 1

Channel 2

WAVEFORM SAMPLING

Channel 1

Signal-to-Noise Plus Distortion

Bandwidth (–3 dB)

Channel 2

Signal-to-Noise Plus Distortion

Bandwidth (–3 dB)

REV. 0

0.2

% typ

0.3

% typ

V max

kΩ min

kHz

% typ

mV max

dB typ

kHz

dB typ

ENERGY MEASUREMENT ACCURACY

Measurement Bandwidth

Measurement Error

on Channel 1

Channel 1 Range = 1 V Full Scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Channel 1 Range = 0.5 V Full Scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Channel 1 Range = 0.25 V Full Scale

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Phase Error

Between Channels

AC Power Supply Rejection

Output Frequency Variation (CF)

0.1

0.2

0.1

0.2

0.05

0.1

0.2

0.1

0.2

0.05

% typ

–3–

% typ

max

V1 = 1 V dc

V1 = 0.5 V dc

V1 = 0.25 V dc

V2 = 1 V dc

External 2.5 V Reference

Gain = 1, 2, 4, 8, 16

Range = 1 V, Gain = 1

Gain = 1

Over a Dynamic Range 1000 to 1

Line Frequency = 45 Hz to 65 Hz, HPF On

= DV

= 5 V + 175 mV rms/120 Hz

Channel 1 = 20 mV rms/60 Hz, Gain = 16,

Range = 0.5 V

Channel 2 = 175 mV rms/60 Hz, Gain = 4

= DV

= 5 V

250 mV dc

Channel 1 = 20 mV rms/60 Hz, Gain = 16,

Range = 0.5 V

Channel 2 = 175 mV rms/60 Hz, Gain = 4

See Analog Inputs Section

V1P, V1N, V2N and V2P to AGND

CLKIN/256, CLKIN = 3.579545 MHz

External 2.5 V Reference, Gain = 1 on

Channel 1 and 2

Sampling CLKIN/128, 3.579545 MHz/128 =

27.9 kSPS

See Channel 1 Sampling

700 mV rms/60 Hz, Range = 1 V, Gain = 1

CLKIN = 3.579545 MHz

See Channel 2 Sampling

300 mV rms/60 Hz, Gain = 2

CLKIN = 3.579545 MHz

ADE7756–SPECIFICATIONS

Parameter

REFERENCE INPUT

REF

IN/OUT

Input Voltage Range

Input Capacitance

ON-CHIP REFERENCE

Reference Error

Load Current

Output Impedance

Temperature Coefficient

CLKIN

Input Clock Frequency

LOGIC INPUTS

RESET,

DIN, SCLK, CLKIN and

Input High Voltage, V

INH

Input Low Voltage, V

INL

Input Current, I

Input Capacitance, C

LOGIC OUTPUTS

SAG and IRQ

Output High Voltage, V

Output Low Voltage, V

ZX and DOUT

Output High Voltage, V

Output Low Voltage, V

Output High Voltage, V

Output Low Voltage, V

POWER SUPPLY

A Version

2.6

2.2

200

B Version

2.6

2.2

200

Unit

V max

V min

pF max

mV max

µA

max

kΩ min

ppm/°C typ

ppm/°C max

Note All Specifications CLKIN of 3.579545 MHz

MHz max

MHz min

Test Conditions/Comments

2.4 V + 8%

2.4 V – 8%

Nominal 2.4 V at REF

IN/OUT

2.4

0.8

2.4

0.8

V min

V max

µA

max

pF max

0.4

4.75

5.25

4.75

5.25

4.75

5.25

4.75

5.25

Specifications subject to change without notice

–4–

NOTES

See Terminology section for explanation of specifications.

See plots in Typical Performance Characteristic curves.

See Analog Inputs section.

0.4

V min

V max

V min

V max

V min

V max

V min

V max

V min

V max

mA max

SOURCE

= 5 mA

SINK

= 0.8 mA

SOURCE

= 5 mA

SINK

= 7 mA

For Specified Performance

5 V – 5%

5 V + 5%

5 V – 5%

5 V + 5%

Typically 2.0 mA

Typically 3.0 mA

= 5 V

Typically 10 nA, V

= 0 V to DV

Open Drain Outputs, 10 kΩ Pull-Up Resistor

SOURCE

= 5 mA

SINK

= 0.8 mA

REV. 0

ADE7756

TIMING CHARACTERISTICS

1, 2

Parameter

Write Timing

Read Timing

113

124

134

A, B Versions

150

6.4

100

Unit

ns (min)

µs

(min)

µs

(min)

ns (min)

µs

(min)

µs

(min)

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

(AV

= DV

= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz

XTAL, T

MIN

to T

MAX

= –40 C to +85 C, unless otherwise noted.)

Test Conditions/Comments

falling edge to first SCLK falling edge.

SCLK logic high pulsewidth.

SCLK logic low pulsewidth.

Valid Data Setup time before falling edge of SCLK.

Data Hold time after SCLK falling edge.

Minimum time between the end of data byte transfers.

Minimum time between byte transfers during a serial write.

Hold time after SCLK falling edge.

Minimum time between read command (i.e., a write to Communication

Minimum time between data byte transfers during a multibyte read.

Data access time after SCLK rising edge following a write to the

Communications Register.

Bus relinquish time after falling edge of SCLK.

Bus relinquish time after rising edge of

CS.

Specifications subject to change without notice.

OUTPUT

50pF

NOTES

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to

90%) and timed from a voltage level of 1.6 V.

See timing diagram below and Serial Interface section of this data sheet.

Measured with the load circuit in

Load Circuit for Timing Specifications

and defined as the time required for the output to cross 0.8 V or 2.4 V.

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured

number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics

is the true bus relinquish time of the part and is independent of the bus loading.

Figure 1. Load Circuit for Timing Specifications

SCLK

DIN

DB7

DB0

200 A

2.1V

1.6mA

COMMAND BYTE

MOST SIGNIFICANT BYTE

Figure 2. Serial Write Timing

SCLK

DIN

DOUT

COMMAND BYTE

DB7

MOST SIGNIFICANT BYTE

Figure 3. Serial Read Timing

REV. 0

–5–

DB7

DB0

LEAST SIGNIFICANT BYTE

DB0

DB7

DB0

LEAST SIGNIFICANT BYTE