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FEATURES

ADF4216: 550 MHz/1.2 GHz

ADF4217: 550 MHz/2.0 GHz

ADF4218: 550 MHz/2.5 GHz

2.7 V to 5.5 V Power Supply

Selectable Charge Pump Currents

Selectable Dual Modulus Prescaler

IF: 8/9 or 16/17

RF: 32/33 or 64/65

3-Wire Serial Interface

Power-Down Mode

Dual RF PLL Frequency Synthesizers

ADF4216/ADF4217/ADF4218

GENERAL DESCRIPTION

OBS

N = BP + A

PRESCALER

REF

OSCILLATOR

CLOCK

DATA

22-BIT

DATA

N = BP + A

APPLICATIONS

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless LANS

Communications Test Equipment

CATV Equipment

OLE

FUNCTIONAL BLOCK DIAGRAM

The ADF4216/ADF4217/ADF4218 are dual frequency synthe-

sizers that can be used to implement local oscillators (LOs) in

the upconversion and downconversion sections of wireless

receivers and transmitters. They can provide the LO for both

the RF and IF sections. They consist of a low-noise digital PFD

(Phase Frequency Detector), a precision charge pump, a pro-

grammable reference divider, programmable A and B counters,

and a dual-modulus prescaler (P/P+1). The A (6-bit) and B

(11-bit) counters, in conjunction with the dual modulus prescaler

(P/P+1), implement an N divider (N = BP + A). In addition,

the 14-bit reference counter (R Counter), allows selectable

REFIN frequencies at the PFD input. A complete PLL (Phase-

Locked Loop) can be implemented if the synthesizers are

used with an external loop ﬁlter and VCOs (Voltage Con-

trolled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.

The devices operate with a power supply ranging from 2.7 V

to 5.5 V and can be powered down when not in use.

ADF4216/ADF4217/ADF4218

11-BIT IF

B-COUNTER

PHASE

COMPARATOR

CHARGE

PUMP

6-BIT IF

A-COUNTER

LOCK

DETECT

14-BIT IF

R-COUNTER

OUTPUT

MUX

SDOUT

MUXOUT

14-BIT IF

R-COUNTER

LOCK

DETECT

11-BIT RF

B-COUNTER

PRESCALER

6-BIT RF

A-COUNTER

PHASE

COMPARATOR

CHARGE

PUMP

DGND

AGND

DGND

AGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

(V 1 = V 2 =

ADF4216/ADF4217/ADF4218–SPECIFICATIONS

otherwise noted.) 3 V

V 1, V 2 V 1, V 2 6.0 V ; AGND = DGND = AGND = DGND = 0 V; T = T to T unless

MIN

MAX

10%, 5 V

10%;

arameter

RF/IF CHARACTERISTICS (3 V)

RF Input Frequency (RF

)

ADF4216

ADF4217

ADF4218

IF Input Frequency (IF

)

RF Input Sensitivity

IF Input Sensitivity

Maximum Allowable

Prescaler Output Frequency

RF/IF CHARACTERISTICS (5 V)

RF Input Frequency (RF

)

ADF4216

ADF4217

ADF4218

IF Input Frequency (IF

)

RF Input Sensitivity

IF Input Sensitivity

Maximum Allowable

Prescaler Output Frequency

REFIN CHARACTERISTICS

REFIN Input Frequency

REFIN Input Sensitivity

REFIN Input Capacitance

REFIN Input Current

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

Sink/Source

High Value

Low Value

Absolute Accuracy

Three-State Leakage Current

Sink and Source Current Matching

vs. V

vs. Temperature

LOGIC INPUTS

INH

, Input High Voltage

INL

, Input Low Voltage

INH

INL

, Input Current

, Input Capacitance

Oscillator Input Current

LOGIC OUTPUTS

, Output High Voltage

, Output Low Voltage

POWER SUPPLIES

B Version

B Chips

Unit

Test Conditions/Comments

See Figure 3 for Input Circuit.

For lower frequency operation (below the

minimum stated) use a square wave source.

0.2/1.2

0.2/2.0

0.5/2.5

45/550

–15/+4

–10/+4

165

0.2/1.2

0.2/2.0

0.5/2.5

45/550

–15/+4

–10/+4

165

GHz min/max

MHz min/max

dBm min/max

MHz max

OBS

0.2/1.2

0.2/2.0

0.5/2.5

25/550

–15/+4

–10/+4

200

5/40

0.5

100

4.5

1.125

0.8

0.2

100

– 0.4

0.4

2.7/5.5

1/6.0

OLE

200

MHz max

5/40

MHz min/max

0.5

V p-p min

pF max

µA

max

For f < 5 MHz, use dc-coupled square wave

(0 to V

AC-Coupled. When DC-Coupled:

0 to V

max (CMOS-Compatible)

100

MHz max

4.5

1.125

0.8

0.2

100

– 0.4

0.4

2.7/5.5

1/6.0

mA typ

% typ

nA typ

% typ

% max

% typ

V min

V max

µA

max

pF max

µA

max

V min

V max

V min/V max

6.0 V

= 500

µA

= 500

µA

0.5 V V

= V

– 0.5 V

0.2/1.2

0.2/2.0

0.5/2.5

25/550

–15/+4

–10/+4

GHz min/max

MHz min/max

dBm min/max

See Figure 3 for Input Circuit.

For lower frequency operation (below the

minimum stated) use a square wave source.

–2–

REV. 0

ADF4216/ADF4217/ADF4218

Parameter

POWER SUPPLIES (Continued)

(RF + IF)

ADF4216

ADF4217

ADF4218

(RF Only)

ADF4216

ADF4217

ADF4218

(IF Only)

ADF4216

ADF4217

ADF4218

1 + I

Low-Power Sleep Mode

NOISE CHARACTERISTICS

Phase Noise Floor

B Version

B Chips

Unit

Test Conditions/Comments

See TPC 22 and TPC 23

9.0 mA typical at V

= 3 V and T

= 25°C

12 mA typical at V

= 3 V and T

= 25°C

14 mA typical at V

= 3 V and T

= 25°C

5.0 mA typical at V

= 3 V and T

= 25°C

7.0 mA typical at V

= 3 V and T

= 25°C

9.0 mA typical at V

= 3 V and T

= 25°C

4.5 mA typical at V

= 3 V and T

= 25°C

4.5 mA typical at V

= 3 V and T

= 25°C

4.5 mA typical at V

= 3 V and T

= 25°C

0.5

µA

typical

@ 25 kHz PFD Frequency

@ 200 kHz PFD Frequency

@ VCO Output

@ 1 kHz Offset and 200 kHz PFD Frequency

@ 300 Hz Offset and 30 kHz PFD Frequency

@ 1 kHz Offset and 200 kHz PFD Frequency

@ 200 Hz Offset and 10 kHz PFD Frequency

@ 1 kHz Offset and 200 kHz PFD Frequency

0.6

4.5

0.6

–171

–164

mA max

µA

max

dBc/Hz typ

OBS

Phase Noise Performance

ADF4216, ADF4217, ADF4218 (IF)

ADF4216 (RF): 900 MHz Output

ADF4217 (RF): 900 MHz Output

ADF4218 (RF): 900 MHz Output

ADF4216 (RF): 836 MHz Output

ADF4217 (RF): 1750 MHz Output

ADF4218 (RF): 1960 MHz Output

Spurious Signals

ADF4216 ADF4217, ADF4218 (IF)

ADF4216 (RF): 900 MHz Output

ADF4217 (RF): 900 MHz Output

ADF4218 (RF): 900 MHz Output

ADF4216 (RF): 836 MHz Output

ADF4217 (RF): 1750 MHz Output

ADF4218 (RF): 1960 MHz Output

–91

–87

–88

–90

–78

–85

–66

–84

–171

–164

–97/–106

–98/–106

–91/–100

–80/–84

–88/–90

–65/–73

–80/–84

OLE

–91

–87

–88

–90

–78

–85

–66

–84

dBc/Hz typ

dB typ

–97/–106

–98/–106

–91/–100

–80/–84

–88/–90

–65/–73

–80/–84

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

@ 30 kHz/60 kHz and 30 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

@ 10 kHz/20 kHz and 10 kHz PFD Frequency

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

Operating temperature range is as follows: B Version: –40°C to +85°C.

The B Chip speciﬁcations are given as typical values.

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is

less than this value.

1 = V

2 = 3 V; For V

1 = V

2 = 5 V, use CMOS-compatible levels.

Guaranteed by design. Sample tested to ensure compliance.

P = 16; RF

= 900 MHz; IF

= 540 MHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer (f

REFOUT

= 10 MHz @ 0 dBm).

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 540 MHz; N = 2700; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 900 MHz; N = 4500; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 30 kHz; Offset frequency = 300 Hz; f

= 836 MHz; N = 27867; Loop B/W = 3 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 1750 MHz; N = 8750; Loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 10 kHz; Offset frequency = 200 Hz; f

= 1750 MHz; N = 175000; Loop B/W = 1 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; Offset frequency = 1 kHz; f

= 1960 MHz; N = 9800; Loop B/W = 20 kHz.

Speciﬁcations subject to change without notice.

REV. 0

–3–

ADF4216/ADF4217/ADF4218

TIMING CHARACTERISTICS

Parameter

Limit at

MIN

to T

MAX

(B Version)

1 = V

2 = 3 V 10%, 5 V 10%; V

1, V

2 = V

, 5 V

= T

MIN

to T

MAX

unless otherwise noted.)

10%; AGND = DGND = 0 V;

Unit

ns min

Test Conditions/Comments

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulsewidth

OBS

CLOCK

NOTES

Guaranteed by design but not production tested.

Speciﬁcation subject to change without notice.

DATA

DB21 (MSB)

DB20

ABSOLUTE MAXIMUM RATINGS

1, 2

= 25°C unless otherwise noted)

1 to GND

. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1 to V

2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

1, V

2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1, V

2 to V

1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

Digital I/O Voltage to GND . . . . . . –0.3 V to DV

+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

+ 0.3 V

REF

, RF

A, RF

A, IF

B to GND . . . . . . . . . . . –0.3 V to V

+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

OLE

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

Figure 1. Timing Diagram

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling

and assembly.

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

ORDERING GUIDE

Model

ADF4216BRU

ADF4217BRU

ADF4218BRU

Temperature Range

–40°C to +85°C

Package Description

Thin Shrink Small Outline Package (TSSOP)

Package Option*

RU-20

*Contact

the factory for chip availability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADF4216/ADF4217/ADF4218 features proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

ADF4216/ADF4217/ADF4218

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic

Function

Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be

placed as close as possible to this pin. V

1 should have a value of between 2.7 V and 5.5 V. V

1 must

have the same potential as V

Power Supply for the RF Charge Pump. This should be greater than or equal to V

Output from the RF Charge Pump. When enabled this provides

to the external loop ﬁlter, which in

turn drives the external VCO.

Ground Pin for the RF Digital Circuitry.

Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF.

Ground Pin for the RF Analog Circuitry.

Reference Input. This is a CMOS input with a nominal threshold of V

/2 and an equivalent input resis-

tance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.

Ground Pin for the IF Digital (Interface and Control Circuitry).

This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Fre-

quency to be accessed externally. See Table V.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB ﬁrst with the two LSBs being the control bits. This input is

a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.

Ground Pin for the IF Analog Circuitry.

Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF.

Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.

Ground Pin for the IF Digital, Interface, and Control Circuitry.

Output from the IF Charge Pump. When enabled this provides

to the external loop ﬁlter, which in turn

drives the external VCO.

Power Supply for the IF Charge Pump. This should be greater than or equal to V

Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog

ground plane should be placed as close as possible to this pin. V

2 should have a value of between 2.7 V

and 5.5 V. V

2 must have the same potential as V

DGND

AGND

REF

OBS

DGND

MUXOUT

CLK

DATA

AGND

DGND

OLE

PIN CONFIGURATION

DGND

RF 4

AGND

RF 7

REF

IN 8

DGND

TSSOP

DGND

ADF4216/

ADF4217/

ADF4218

AGND

DATA

CLK

MUXOUT

REV. 0

–5–

型号	ADF4217BRU-REEL	ADF4218BRU-REEL7	ADF4217BRU-REEL7	ADF4218BRU-REEL
描述	IC PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circuit	IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20, TSSOP-20, PLL or Frequency Synthesis Circuit
是否Rohs认证	不符合	不符合	不符合	不符合
零件包装代码	TSSOP	TSSOP	TSSOP	TSSOP
包装说明	TSSOP-20	TSSOP-20	TSSOP-20	TSSOP-20
针数	20	20	20	20
Reach Compliance Code	not_compliant	not_compliant	unknown	unknown
ECCN代码	5A991.B	5A991.B	5A991.B	5A991.B
其他特性	DUAL MODULUS PRESCALER (RF): 32/33 OR 64/65 AND DUAL MODULUS PRESCALER (IF): 8/9, 16/17	DUAL MODULUS PRESCALER (RF): 32/33 OR 64/65 AND DUAL MODULUS PRESCALER (IF): 8/9, 16/17	DUAL MODULUS PRESCALER (RF): 32/33 OR 64/65 AND DUAL MODULUS PRESCALER (IF): 8/9, 16/17	DUAL MODULUS PRESCALER (RF): 32/33 OR 64/65 AND DUAL MODULUS PRESCALER (IF): 8/9, 16/17
模拟集成电路 - 其他类型	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER
JESD-30 代码	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609代码	e0	e0	e0	e0
长度	6.5 mm	6.5 mm	6.5 mm	6.5 mm
功能数量	1	1	1	1
端子数量	20	20	20	20
最高工作温度	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	TSSOP	TSSOP	TSSOP
封装等效代码	TSSOP20,.25	TSSOP20,.25	TSSOP20,.25	TSSOP20,.25
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	3/5 V	3/5 V	3/5 V	3/5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.1 mm	1.1 mm	1.1 mm	1.1 mm
最大供电电流 (Isup)	4.5 mA	5 mA	4.5 mA	5 mA
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
标称供电电压 (Vsup)	3 V	3 V	3 V	3 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	TIN LEAD	Tin/Lead (Sn/Pb)	TIN LEAD	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	4.4 mm	4.4 mm	4.4 mm	4.4 mm