a
FEATURES
Single Chip Low Power UHF Transmitter
902 MHz–928 MHz Frequency Band
On-Chip VCO and Fractional-N PLL
2.3 V–3.6 V Supply Voltage
Programmable Output Power
–16 dBm to +12 dBm, 0.3 dB Steps
Data Rates up to 76.8 kbps
Low Current Consumption
28 mA at 8 dBm Output
Power-Down Mode (<1 A)
24-Lead TSSOP Package
APPLICATIONS
Low Cost Wireless Data Transfer
Wireless Metering
Remote Control/Security Systems
Keyless Entry
High Performance ISM Band
ASK/FSK/GFSK Transmitter IC
ADF7010
GENERAL DESCRIPTION
The ADF7010 is a low power OOK/ASK/FSK/GFSK UHF
transmitter designed for use in ISM band systems. It contains
an integrated VCO and sigma-delta fractional-N PLL. The
output power, channel spacing, and output frequency are pro-
grammable with four 24-bit registers. The fractional-N PLL
enables the user to select any channel frequency within the U.S.
902 MHz–928 MHz band, allowing the use of the ADF7010 in
frequency hopping systems.
It is possible to choose from the four different modulation
schemes: Binary or Gaussian Frequency Shift Keying (FSK/
GFSK), Amplitude Shift Keying (ASK), or On/Off Keying
(OOK). The device also features a crystal compensation register
that can provide 1 ppm resolution in the output frequency.
Indirect temperature compensation of the crystal can be accom-
plished inexpensively using this register.
Control of the four on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.3 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
C
REG
OSC1
OSC2
CLK
OUT
CPV
DD
CP
GND
C
VCO
VCO
GND
CLK
OOK/ASK
V
DD
VCO
DV
DD
PA
RF
OUT
RF
GND
R
PFD/
CHARGE
PUMP
C
REG
LDO
REGULATOR
FRACTIONAL N
FSK/GFSK
SIGMA-DELTA
LOCK DETECT
D
GND
OOK/ASK
TxCLK
TxDATA
LE
DATA
CLK
CE
SERIAL
INTERFACE
FREQUENCY
COMPENSATION
CENTER
FREQUENCY
MUXOUT
MUXOUT
R
SET
A
GND
TEST
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADF7010–SPECIFICATIONS
Parameter
RF CHARACTERISTICS
Output Frequency Ranges
U.S. ISM Band
Phase Frequency Detector Frequency
TRANSMISSION PARAMETERS
Transmit Rate
FSK
ASK
GFSK
Frequency Shift Keying
FSK Separation
2, 3
Gaussian Filter t
Amplitude Shift Keying Depth
On/Off Keying
Output Power
Output Power Variation
Max Power Setting
Min
902
3.625
1
(V
DD
= 2.3 V to 3.6 V, GND = 0 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
specifications are at V
DD
= 3 V, T
A
= 25 C.)
Typ
Max
Unit
928
20
MHz
MHz @ 928 MHz
0.3
0.3
0.3
1
4.88
0.5
76.8
9.6
76.8
110
620
30
40
kbps
kbps
kbps
kHz, Using 3.625 MHz PFD
kHz, Using 20 MHz PFD
dB, Max Output Power 2 dBm
dB
9
12
11
9.5
0.3125
dBm, V
DD
= 3.6 V
dBm, V
DD
= 3.0 V
dBm, V
DD
= 2.3 V
dB
V
V
mA
pF
MHz
V, I
OH
= 500
mA
V, I
OL
= 500
mA
ns, F
CLK
= 4.8 MHz into 10 pF
Programmable Step Size
–16 dBm to +12 dBm
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
Control Clock Input
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
CLK
OUT
Rise/Fall Time
CLK
OUT
Mark: Space Ratio
POWER SUPPLIES
Voltage Supply
DV
DD
Transmit Current Consumption
–20 dBm (0.01 mW)
–10 dBm (0.1 mW)
0 dBm (1 mW)
+8 dBm (6.3 mW)
+12 dBm (16 mW)
Crystal Oscillator Block Current
Consumption
Regulator Current Consumption
Power-Down Mode
Low Power Sleep Mode
0.7
V
DD
0.2
1
10
50
DV
DD
– 0.4
0.4
16
50:50
V
DD
2.3
12
15
20
28
40
190
380
0.2
3.6
V
mA
mA
mA
mA
mA
mA
mA
1
mA
–2–
REV. 0
ADF7010
Parameter
PHASE-LOCKED LOOP
VCO Gain
Phase Noise (In-Band)
4
Phase Noise (Out of Band)
5
Spurious
Integer Boundary
6
Reference
Harmonics
7
Second Harmonic V
DD
= 3.0 V
Third Harmonic V
DD
= 3.0 V
All Other Harmonics
REFERENCE INPUT
Crystal Reference
External Oscillator
Input Level, High Voltage
Input Level, Low Voltage
FREQUENCY COMPENSATION
Pull In Range of Register
PA CHARACTERISTICS
RF Output Impedance
High Range Amplifier
TIMING INFORMATION
Chip Enabled to Regulator Ready
7
Crystal Oscillator to CLK
OUT
OK
TEMPERATURE RANGE, T
A
–40
3.625
3.625
0.7 V
DD
Min
Typ
80
–80
–100
–55
–50
–27
–21
–14
–18
–18
–35
20
40
0.2
1
100
V
DD
Max
Unit
MHz/V @ 915 MHz
dBc/Hz @ 5 kHz Offset
dBc/Hz @ 1 MHz Offset
100 kHz Loop BW
dBc, 50 kHz Loop
dBc
dBc
dBc
dBc
dBc
MHz
MHz
V
V
ppm
16 – j33
50
2
200
+85
W,
Z
REF
= 50
W
ms
ms, 19.2 MHz Xtal
C
NOTES
1
Operating temperature range is as follows: –40∞C to +85∞C.
2
Frequency Deviation = (PFD Frequency Mod Deviation )/2
12
.
3
GFSK Frequency Deviation = (PFD Frequency 2
m
)/2
12
where
m
= Mod Control.
4
V
DD
= 3 V, PFD = 19.2 MHz, PA = 8 dBm
5
V
DD
= 3 V, Loop Filter BW = 100 kHz
6
Measured >1 MHz away from integer channel. See
Successful Design with ADF7010 Transmitter
application note.
7
Not production tested. Based on characterization.
Specifications subject to change without notice.
REV. 0
–3–
ADF7010
TIMING CHARACTERISTICS
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
DD
=
3V
10%, VGND = 0 V, T
A
= 25 C, unless otherwise noted.)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
t
3
t
4
CLOCK
t
1
t
2
DATA
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
<1 kV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = CPGND = RFGND = DGND = AGND = 0 V.
V
DD
to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V
VCOVDD, RFVDD, CPVDD to GND . . . . . –0.3 V to +7 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +125∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C
TSSOP
JA
Thermal Impedance . . . . . . . . . . . . . . 150.4∞C/W
CSP
JA
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . 122∞C/W
CSP
JA
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . 216∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C
(T
A
= 25∞C, unless otherwise noted.)
ORDERING GUIDE
Model
ADF7010BRU
Temperature Range
–40ºC to +85ºC
Package Option
RU-24 (TSSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF7010 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
ADF7010
PIN CONFIGURATION
R
SET 1
CPV
DD 2
CP
GND
3
24
C
REG
23
C
VCO
22
VCO
IN
CP
OUT 4
CE
5
DATA
CLK
LE
6
7
8
TSSOP
21
A
GND
20
RF
OUT
19
RF
GND
18
DV
DD
17
TEST
16
VCO
GND
15
OSC1
14
OSC2
13
CLK
OUT
ADF7010
TOP VIEW
(Not to Scale)
TxDATA
9
TxCLK
10
MUXOUT
11
D
GND 12
PIN FUNCTION DESCRIPTIONS
Pin No.
1
Mnemonic
R
SET
Function
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 4.7 kW as default:
I
CP MAX
=
9.5
R
SET
So, with R
SET
= 4.7 kW, I
CPMAX
= 2.02 mA.
2
3
4
5
6
7
8
9
10
11
12
13
CPV
DD
CP
GND
CP
OUT
CE
DATA
CLK
LE
TxDATA
TxCLK
MUXOUT
D
GND
CLK
OUT
Charge Pump Supply. This should be biased at the same level as RFV
DD
and DV
DD
. The pin should be
decoupled with a 0.1
mF
capacitor as close to the pin as possible.
Charge Pump Ground
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
Chip Enable. A logic low applied to this pin powers down the part. This must be high for the part to
function. This is the only way to power down the regulator circuit.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This is a high impedance CMOS input.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
Digital data to be transmitted is input on this pin.
GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the
ADF7010. The clock is provided at the same frequency as the data rate.
This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled
reference frequency to be accessed externally. Used commonly for system debug. See Function Register Map.
Ground Pin for the RF Digital Circuitry
The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock input
of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can be
reduced with a series RC. For 4.8 MHz output clock, a series 50
W
into 10 pF will reduce spurs to
< –50 dBc. Defaults on power-up to divide by 16.
Oscillator Pin. If a single-ended reference is used (such as a TCXO), it should be applied to this pin.
When using an external signal generator, a 51
W
resistor should be tied from this pin to ground. The
XOE
bit in the R Register should set high when using an external reference.
14
OSC2
REV. 0
–5–
